[AMD Official Use Only - AMD Internal Distribution Only] Hi Prasanth,
> -----Original Message----- > From: Neha Malcom Francis <n-fran...@ti.com> > Sent: Wednesday, July 16, 2025 1:11 PM > To: Prasanth Babu Mantena <p-mant...@ti.com>; tr...@konsulko.com; > s...@chromium.org; alpernebiya...@gmail.com; Simek, Michal > <michal.si...@amd.com> > Cc: u-boot@lists.denx.de; Abbarapu, Venkatesh <venkatesh.abbar...@amd.com>; > vigne...@ti.com; u-kum...@ti.com; vaishna...@ti.com; s...@ti.com > Subject: Re: [PATCH] Revert "spi: cadence_qspi: Fix odd byte write issue in > STIG > mode" > > Hi Prasanth > > On 16/07/25 12:34, Prasanth Babu Mantena wrote: > > The buffer that is being used to write into the flash needs to be > > handled properly with padding of 0xFF. The place that this is done can > > be at a more generic place like spi-nor core. > > > > This reverts commit cd9123507003e07b13e61d72e14e493bb338e827. > > > > Signed-off-by: Prasanth Babu Mantena <p-mant...@ti.com> > > --- > > drivers/spi/cadence_qspi_apb.c | 3 --- > > 1 file changed, 3 deletions(-) > > > > diff --git a/drivers/spi/cadence_qspi_apb.c > > b/drivers/spi/cadence_qspi_apb.c index 6f89d3add5d..4696c09f754 100644 > > --- a/drivers/spi/cadence_qspi_apb.c > > +++ b/drivers/spi/cadence_qspi_apb.c > > @@ -558,9 +558,6 @@ int cadence_qspi_apb_command_write(struct > cadence_spi_priv *priv, > > void *reg_base = priv->regbase; > > u8 opcode; > > > > - if (priv->dtr) > > - txlen += txlen & 1; > > - > > if (priv->dtr) > > opcode = op->cmd.opcode >> 8; > > else > > After reading [0], makes sense. > > Reviewed-by: Neha Malcom Francis <n-fran...@ti.com> > > [0] > https://lore.kernel.org/u-boot/174963a1-bf6e-4e54-9946-bf3c42a72...@amd.com/ Ok...Will check and handle this in spi-nor core framework itself. Reviewed-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com> Thanks Venkatesh > > -- > Thanking You > Neha Malcom Francis
