Hi Luca,
On 18/06/2025 16:25, Luca Weiss wrote:
> Add Clock driver for the GCC block found in the SM6350 SoC.
>
> Signed-off-by: Luca Weiss <luca.we...@fairphone.com>
> ---
> drivers/clk/qcom/Kconfig | 8 ++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clock-sm6350.c | 194
> ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 203 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index
> 3ea01f3c969a3456a7c2ebf731b8b74b66d93f96..e0e91dadd854e6e3a7beb1ef351734a5ab77787f
> 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -79,6 +79,14 @@ config CLK_QCOM_SM6115
> on the Snapdragon SM6115 SoC. This driver supports the clocks
> and resets exposed by the GCC hardware block.
>
[snip]
> +static ulong sm6350_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> + const struct freq_tbl *freq;
> +
> + if (clk->id < priv->data->num_clks)
> + debug("%s: %s, requested rate=%ld\n", __func__,
> + priv->data->clks[clk->id].name, rate);
> +
> + switch (clk->id) {
> + case GCC_QUPV3_WRAP1_S3_CLK: /*UART9*/
> + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s3_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, GCC_SE12_UART_RCG_REG,
> + freq->pre_div, freq->m, freq->n, freq->src,
> + 16);
> +
> + return freq->freq;
> + case GCC_SDCC2_APPS_CLK:
> + /* Enable GPLL7 so that we can point SDCC2_APPS_CLK_SRC at it */
> + clk_enable_gpll0(priv->base, &gpll7_vote_clk);
> + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
> + printf("%s: got freq %u\n", __func__, freq->freq);
Please drop this printf, then add
Reviewed-by: Casey Connolly <casey.conno...@linaro.org>
I think we'll have to do some kind of improvement around the frequency
selection stuff eventually... Not the end of the world today as we'll at
least get warnings if something goes wrong due to DTS or driver changes.
Kind regards,
--
// Casey (she/her)
