Enable cache for J722s to optimize performance of CPU to access data from memory.
Reviewed-by: Alexander Sverdlin <alexander.sverd...@siemens.com> Signed-off-by: Chintan Vankar <c-van...@ti.com> --- Link to v3: https://lore.kernel.org/u-boot/20250225114903.2080616-14-c-van...@ti.com/ Changes from v3 to v4: - Collected Reviewed-by from Alexander Sverdlin. board/ti/j722s/evm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index d2b94913c12..32d767cb7d2 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -8,6 +8,7 @@ #include <asm/arch/hardware.h> #include <asm/io.h> +#include <cpu_func.h> #include <dm/uclass.h> #include <env.h> #include <fdt_support.h> @@ -15,6 +16,13 @@ #include <asm/arch/k3-ddr.h> #include "../common/fdt_ops.h" +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + enable_caches(); +} +#endif + #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { -- 2.34.1
