From: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@altera.com> Update exisitng Agilex device tree to support multiple flashes boot - MMC, QSPI and NAND.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@altera.com> --- MAINTAINERS | 3 ++- arch/arm/dts/socfpga_agilex.dtsi | 4 ++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 19 +++++++++++++++++++ arch/arm/dts/socfpga_agilex_socdk.dts | 15 ++++++--------- 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2e730f94481..0d03a3a2199 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -155,9 +155,10 @@ M: Tien Fong Chee <tien.fong.c...@altera.com> M: Tingting Meng <tingting.m...@altera.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git +F: arch/arm/dts/socfpga_* +F: arch/arm/mach-socfpga/ F: configs/socfpga_* F: drivers/ddr/altera/ -F: arch/arm/mach-socfpga/ F: drivers/sysreset/sysreset_socfpga* ARM AMLOGIC SOC SUPPORT diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi index 712304d07a4..be5100aea98 100644 --- a/arch/arm/dts/socfpga_agilex.dtsi +++ b/arch/arm/dts/socfpga_agilex.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ /dts-v1/; @@ -308,6 +309,9 @@ <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 97 4>; + clocks = <&clkmgr AGILEX_NAND_CLK>, + <&clkmgr AGILEX_NAND_X_CLK>; + clock-names = "nand", "nand_x"; resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 63df28e8364..f9491d57068 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -3,11 +3,17 @@ * U-Boot additions * * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_agilex-u-boot.dtsi" /{ + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand; + }; + aliases { spi0 = &qspi; i2c0 = &i2c1; @@ -34,12 +40,19 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; bootph-all; + /delete-property/ cdns,read-delay; }; &i2c1 { status = "okay"; }; +&nand { + status = "okay"; + nand-bus-width = <16>; + bootph-all; +}; + &mmc { drvsel = <3>; smplsel = <0>; @@ -53,3 +66,9 @@ &watchdog0 { bootph-all; }; + +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&binman { + /delete-node/ kernel; +}; +#endif diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex_socdk.dts index bcdeecc0e02..9cb9ff9fbc0 100644 --- a/arch/arm/dts/socfpga_agilex_socdk.dts +++ b/arch/arm/dts/socfpga_agilex_socdk.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_agilex.dtsi" @@ -14,10 +15,6 @@ ethernet2 = &gmac2; }; - chosen { - stdout-path = "serial0:115200n8"; - }; - leds { compatible = "gpio-leds"; hps0 { @@ -128,13 +125,13 @@ #size-cells = <1>; qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; + label = "u-boot"; + reg = <0x0 0x04200000>; }; - qspi_rootfs: partition@34B0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; }; }; }; -- 2.35.3
