Fix the incorrect bit masking and bit shift used to compute EMAC
control which in turn is used to select EMAC clock from EMAC
source A or B.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapa...@altera.com>
---
drivers/clk/altera/clk-agilex.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index e1ddd02f356..967d8a41272 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -1,6 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include <log.h>
@@ -515,14 +516,14 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat
*plat, u32 emac_id)
/* Get EMAC clock source */
ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
if (emac_id == AGILEX_EMAC0_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
+ ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >>
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET;
else if (emac_id == AGILEX_EMAC1_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
+ ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >>
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET;
else if (emac_id == AGILEX_EMAC2_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
+ ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >>
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET;
else
return 0;
--
2.35.3
