On 8/22/25 02:48, Hal Feng wrote:
>> On 20.08.25 10:45 E Shattow wrote:
>> On 8/17/25 23:45, Hal Feng wrote:
>>>> On 15.08.25 13:03, E Shattow wrote:
>>>> Prune jh7110-common-u-boot.dtsi (clocks, qspi flash, eeprom, and
>>>> bootph- pre-ram hints now upstream since devicetree-rebasing v6.16)
>>>> and replace by remaining dependency jh7110-u-boot.dtsi (not yet
>> upstream).
>>>>
>>>> Signed-off-by: E Shattow <e...@freeshell.de>
>>>> ---
>>>> arch/riscv/dts/jh7110-common-u-boot.dtsi | 99 -------------------
>>>> .../jh7110-deepcomputing-fml13v01-u-boot.dtsi | 2 +-
>>>> arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 2 +-
>>>> .../dts/jh7110-pine64-star64-u-boot.dtsi | 2 +-
>>>> ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 2 +-
>>>> ...10-starfive-visionfive- 2-v1.3b-u-boot.dtsi | 2 +-
>>>> 6 files changed, 5 insertions(+), 104 deletions(-) delete mode
>>>> 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
>>>>
>>>> diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi
>>>> b/arch/riscv/dts/jh7110-common-u-boot.dtsi
>>>> deleted file mode 100644
>>>> index 049b0a7ce28..00000000000
>>>> --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi
>>>> +++ /dev/null
>>>> @@ -1,99 +0,0 @@
>>>> -// SPDX-License-Identifier: GPL-2.0 OR MIT
>>>> -/*
>>>> - * Copyright (C) 2023 StarFive Technology Co., Ltd.
>>>> - */
>>>> -
>>>> -#include "jh7110-u-boot.dtsi"
>>>> -/ {
>>>> - aliases {
>>>> - spi0 = &qspi;
>>>> - };
>>>> -
>>>> - chosen {
>>>> - bootph-pre-ram;
>>>> - };
>>>> -
>>>> - firmware {
>>>> - spi0 = &qspi;
>>>> - bootph-pre-ram;
>>>> - };
>>>> -
>>>> - memory@40000000 {
>>>> - bootph-pre-ram;
>>>> - };
>>>> -};
>>>> -
>>>> -&uart0 {
>>>> - bootph-pre-ram;
>>>> - reg-offset = <0>;
>>>> - current-speed = <115200>;
>>>> -};
>>>> -
>>>> -&mmc0 {
>>>> - bootph-pre-ram;
>>>> -};
>>>> -
>>>> -&mmc1 {
>>>> - bootph-pre-ram;
>>>> -};
>>>> -
>>>> -&qspi {
>>>> - bootph-pre-ram;
>>>> -
>>>> - flash@0 {
>>>> - bootph-pre-ram;
>>>> - cdns,read-delay = <2>;
>>>> - spi-max-frequency = <100000000>;
>>>> - };
>>>> -};
>>>> -
>>>> -&syscrg {
>>>> - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
>>>> - <&syscrg JH7110_SYSCLK_BUS_ROOT>,
>>>> - <&syscrg JH7110_SYSCLK_PERH_ROOT>,
>>>> - <&syscrg JH7110_SYSCLK_QSPI_REF>;
>>>> - assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
>>>> - <&pllclk JH7110_PLLCLK_PLL2_OUT>,
>>>> - <&pllclk JH7110_PLLCLK_PLL2_OUT>,
>>>> - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
>>>> - assigned-clock-rates = <0>, <0>, <0>, <0>;
>>>> -};
>>>> -
>>>> -&sysgpio {
>>>> - bootph-pre-ram;
>>>> -};
>>>> -
>>>> -&mmc0_pins {
>>>> - bootph-pre-ram;
>>>> - rst-pins {
>>>> - bootph-pre-ram;
>>>> - };
>>>> -};
>>>> -
>>>> -&mmc1_pins {
>>>> - bootph-pre-ram;
>>>> - clk-pins {
>>>> - bootph-pre-ram;
>>>> - };
>>>> -
>>>> - mmc-pins {
>>>> - bootph-pre-ram;
>>>> - };
>>>> -};
>>>> -
>>>> -&i2c5_pins {
>>>> - bootph-pre-ram;
>>>> - i2c-pins {
>>>> - bootph-pre-ram;
>>>> - };
>>>> -};
>>>> -
>>>> -&i2c5 {
>>>> - bootph-pre-ram;
>>>> - eeprom@50 {
>>>> - bootph-pre-ram;
>>>> - compatible = "atmel,24c04";
>>>> - reg = <0x50>;
>>>> - pagesize = <16>;
>>>> - };
>>>> -};
>>>> diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
>>>> b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
>>>> index ab882d07f6f..b9202f2acce 100644
>>>> --- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
>>>> +++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
>>>> @@ -3,5 +3,5 @@
>>>> * Copyright (C) 2024 StarFive Technology Co., Ltd.
>>>> */
>>>>
>>>> -#include "jh7110-common-u-boot.dtsi"
>>>> +#include "jh7110-u-boot.dtsi"
>>>> #include "starfive-visionfive2-binman.dtsi"
>>>> diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
>>>> b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
>>>> index ab882d07f6f..b9202f2acce 100644
>>>> --- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
>>>> +++ b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
>>>> @@ -3,5 +3,5 @@
>>>> * Copyright (C) 2024 StarFive Technology Co., Ltd.
>>>> */
>>>>
>>>> -#include "jh7110-common-u-boot.dtsi"
>>>> +#include "jh7110-u-boot.dtsi"
>>>> #include "starfive-visionfive2-binman.dtsi"
>>>> diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
>>>> b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
>>>> index ab882d07f6f..b9202f2acce 100644
>>>> --- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
>>>> +++ b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
>>>> @@ -3,5 +3,5 @@
>>>> * Copyright (C) 2024 StarFive Technology Co., Ltd.
>>>> */
>>>>
>>>> -#include "jh7110-common-u-boot.dtsi"
>>>> +#include "jh7110-u-boot.dtsi"
>>>> #include "starfive-visionfive2-binman.dtsi"
>>>> diff --git
>>>> a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
>>>> b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
>>>> index ab882d07f6f..b9202f2acce 100644
>>>> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
>>>> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
>>>> @@ -3,5 +3,5 @@
>>>> * Copyright (C) 2024 StarFive Technology Co., Ltd.
>>>> */
>>>>
>>>> -#include "jh7110-common-u-boot.dtsi"
>>>> +#include "jh7110-u-boot.dtsi"
>>>> #include "starfive-visionfive2-binman.dtsi"
>>>> diff --git
>>>> a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
>>>> b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
>>>> index 874074174ff..848ed8225ac 100644
>>>> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
>>>> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
>>>> @@ -3,5 +3,5 @@
>>>> * Copyright (C) 2023 StarFive Technology Co., Ltd.
>>>> */
>>>>
>>>> -#include "jh7110-common-u-boot.dtsi"
>>>> +#include "jh7110-u-boot.dtsi"
>>>> #include "starfive-visionfive2-binman.dtsi"
>>>>
>>>> base-commit: 0c558bbad9e7581808b358091d1fd979f860e8ac
>>>
>>> I find that there are no ''bootph-pre-ram'' in mmc0_pins and mmc1_pins
>>> in dts/upstream/src/riscv/starfive/jh7110-common.dtsi.
>>>
>>> Is it ready now to drop jh7110-common-u-boot.dtsi?
>>>
>>> Best regards,
>>> Hal
>>
>> Yes, thank you for your review.
>>
>> Currently the U-Boot SPL code path that requires eMMC and SD Card
>> functionality is with these deprecated JH7110 loader modes, or some unlikely
>> runtime change in RGPIO0 / RGPIO1 state before U-Boot SPL following the
>> JH7110 loader.
>>
>> I will consider seriously to support the deprecated functionality if there is
>> sufficient documentation in the form of a full source code listing for the
>> JH7110 mask ROM loader. Otherwise I do not have time or interest to reverse-
>> engineer these things lacking in documentation from StarFive.
>
> You are right. It's suggested to only boot from flash on VF2 board.
>
> But it is weird that in dts/upstream/src/riscv/starfive/jh7110-common.dtsi,
> there are "bootph-pre-ram" in mmc0/1 nodes and no "bootph-pre-ram"
> in mmc0/1_pins nodes.
>
> Best regards,
> Hal
Yes, the half-baked result is from code review and I asked for
supporting documentation also on LKML some months ago ref. v2:
https://lore.kernel.org/lkml/521e5549-de83-49a1-a0e5-e47a2cb27...@freeshell.de/
The test methodology I collected is detailed in the cover letter for v3:
https://lore.kernel.org/lkml/20250502103101.957016-...@freeshell.de/
Simply I applied what was requested in the code review v2 and posted the
test methodology in v3 for others to improve, verify, and comment on.
The series v3 was sent 2nd May and no further comment for two weeks
until applied 15th May.
It would be helpful to know if this mmc use at U-Boot SPL phase is
actually broken or if it is working, as it is with the patch applied
(absent the suggested mmc pins bootph-pre-ram hint). Documentation in
doc/board/starfive/jh7110_common.rst will need to be updated.
-E
