commit: http://blackfin.uclinux.org/git/?p=u-boot;a=commitdiff;h=e045317cf129f32d0888d6daa13908e063776987 branch: http://blackfin.uclinux.org/git/?p=u-boot;a=shortlog;h=refs/heads/trunk
Signed-off-by: Sonic Zhang <sonic.zh...@analog.com> --- arch/blackfin/cpu/initcode.c | 16 +++++-- arch/blackfin/cpu/serial1.h | 38 +++++++++++++---- arch/blackfin/cpu/serial4.h | 6 ++- arch/blackfin/include/asm/cplb.h | 14 +++++-- arch/blackfin/include/asm/mach-common/bits/dma.h | 48 +++++++++++----------- arch/blackfin/include/asm/mach-common/bits/sdh.h | 4 +- arch/blackfin/lib/board.c | 3 +- arch/blackfin/lib/clocks.c | 3 +- drivers/spi/bfin_spi6xx.c | 16 ++++---- include/configs/bf609-ezkit.h | 4 +- 10 files changed, 95 insertions(+), 57 deletions(-) diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 2173b6b..6c3f35b 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -32,7 +32,8 @@ #endif #ifdef __ADSPBF60x__ -#define CONFIG_BFIN_GET_DCLK_M ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000)) +#define CONFIG_BFIN_GET_DCLK_M \ + ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000)) #ifndef CONFIG_DMC_DDRCFG #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \ @@ -167,7 +168,8 @@ static inline void serial_init(void) #if BFIN_UART_HW_VER < 4 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL); #else - bfin_write32(&pUART->control, bfin_read32(&pUART->control) | FCPOL); + bfin_write32(&pUART->control, bfin_read32(&pUART->control) | + FCPOL); #endif /* Wait for the line to clear up. We cannot rely on UART @@ -216,7 +218,8 @@ static inline void serial_deinit(void) #if BFIN_UART_HW_VER < 4 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL); #else - bfin_write32(&pUART->control, bfin_read32(&pUART->control) & ~FCPOL); + bfin_write32(&pUART->control, bfin_read32(&pUART->control) & + ~FCPOL); #endif } #endif @@ -816,7 +819,8 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) continue; - dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET; + dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> + PHYRDPHASE_OFFSET; dll_ctl = bfin_read_DMC0_DLLCTL(); dll_ctl &= 0x0ff; bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); @@ -925,7 +929,9 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) "nop;nop;nop;" "rti;" : - : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */), "d"(0xffa00000) + : "p"(hibernate_magic), + "d"(0x2000 /* jump.s 0 */), + "d"(0xffa00000) ); } diff --git a/arch/blackfin/cpu/serial1.h b/arch/blackfin/cpu/serial1.h index 6614c8b..89c0a7a 100644 --- a/arch/blackfin/cpu/serial1.h +++ b/arch/blackfin/cpu/serial1.h @@ -89,8 +89,14 @@ static inline void serial_early_do_portmux(void) { #if defined(__ADSPBF50x__) # define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_1 | PORT_x_MUX_##mux_rx##_FUNC_1); \ - bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + do { bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & \ + ~(PORT_x_MUX_##mux_tx##_MASK | \ + PORT_x_MUX_##mux_rx##_MASK)) | \ + PORT_x_MUX_##mux_tx##_FUNC_1 | \ + PORT_x_MUX_##mux_rx##_FUNC_1); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | \ + P##port##tx | P##port##rx); \ + } while (0) switch (CONFIG_UART_CONSOLE) { case 0: DO_MUX(G, 7, 7, 12, 13); break; /* Port G; mux 7; PG12 and PG13 */ case 1: DO_MUX(F, 3, 3, 6, 7); break; /* Port F; mux 3; PF6 and PF7 */ @@ -98,8 +104,14 @@ static inline void serial_early_do_portmux(void) SSYNC(); #elif defined(__ADSPBF51x__) # define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \ - bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + do { bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & \ + ~(PORT_x_MUX_##mux_tx##_MASK | \ + PORT_x_MUX_##mux_rx##_MASK)) | \ + PORT_x_MUX_##mux_tx##_FUNC_2 | \ + PORT_x_MUX_##mux_rx##_FUNC_2); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | \ + P##port##tx | P##port##rx); \ + } while (0) switch (CONFIG_UART_CONSOLE) { case 0: DO_MUX(G, 5, 5, 9, 10); break; /* Port G; mux 5; PG9 and PG10 */ case 1: DO_MUX(F, 2, 3, 14, 15); break; /* Port H; mux 2/3; PH14 and PH15 */ @@ -107,8 +119,12 @@ static inline void serial_early_do_portmux(void) SSYNC(); #elif defined(__ADSPBF52x__) # define DO_MUX(port, mux, tx, rx) \ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \ - bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + do { bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & \ + ~PORT_x_MUX_##mux##_MASK) | \ + PORT_x_MUX_##mux##_FUNC_3); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | \ + P##port##tx | P##port##rx); \ + } while (0) switch (CONFIG_UART_CONSOLE) { case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */ case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */ @@ -123,8 +139,14 @@ static inline void serial_early_do_portmux(void) SSYNC(); #elif defined(__ADSPBF54x__) # define DO_MUX(port, tx, rx) \ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \ - bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + do { bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & \ + ~(PORT_x_MUX_##tx##_MASK | \ + PORT_x_MUX_##rx##_MASK)) | \ + PORT_x_MUX_##tx##_FUNC_1 | \ + PORT_x_MUX_##rx##_FUNC_1); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | \ + P##port##tx | P##port##rx); \ + } while (0) switch (CONFIG_UART_CONSOLE) { case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */ case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */ diff --git a/arch/blackfin/cpu/serial4.h b/arch/blackfin/cpu/serial4.h index 8374f47..f3a4051 100644 --- a/arch/blackfin/cpu/serial4.h +++ b/arch/blackfin/cpu/serial4.h @@ -48,7 +48,11 @@ static inline void serial_early_do_portmux(void) #if defined(__ADSPBF60x__) # define DO_MUX(port, tx, rx, func) do \ {\ - bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_##func | PORT_x_MUX_##rx##_FUNC_##func); \ + bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & \ + ~(PORT_x_MUX_##tx##_MASK | \ + PORT_x_MUX_##rx##_MASK)) | \ + PORT_x_MUX_##tx##_FUNC_##func | \ + PORT_x_MUX_##rx##_FUNC_##func); \ bfin_write_PORT##port##_FER_SET(P##port##tx | P##port##rx);\ } while (0); switch (CONFIG_UART_CONSOLE) { diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index 5a0588b..33b1698 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -47,9 +47,11 @@ /* Data Attibutes*/ #if defined(__ADSPBF60x__) -#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | \ + CPLB_USER_RD | CPLB_VALID) #else -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | \ + CPLB_USER_RD | CPLB_VALID) #endif #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) @@ -63,9 +65,13 @@ #ifdef CONFIG_DCACHE_WB /*Write Back Policy */ #if defined(__ADSPBF60x__) -#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \ + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \ + CPLB_VALID | ANOMALY_05000158_WORKAROUND) #else -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \ + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \ + CPLB_VALID | ANOMALY_05000158_WORKAROUND) #endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) diff --git a/arch/blackfin/include/asm/mach-common/bits/dma.h b/arch/blackfin/include/asm/mach-common/bits/dma.h index 1126c44..ac426ad 100644 --- a/arch/blackfin/include/asm/mach-common/bits/dma.h +++ b/arch/blackfin/include/asm/mach-common/bits/dma.h @@ -23,27 +23,27 @@ #define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */ #define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */ #define RESTART 0x00000004 /* DMA Buffer Clear SYNC */ -#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */ -#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */ -#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */ -#define DI_EN DI_EN_X /* Data Interrupt Enable */ -#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 6 */ -#define NDSIZE 0x00070000 /* Next Descriptor Size */ -#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */ -#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */ -#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */ -#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */ -#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */ -#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */ -#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */ -#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */ -#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */ +#define DI_EN_X 0x00100000 /* Data Int Enable in X count */ +#define DI_EN_Y 0x00200000 /* Data Int Enable in Y count */ +#define DI_EN_P 0x00300000 /* Data Int Enable in Peri */ +#define DI_EN DI_EN_X /* Data Int Enable */ +#define NDSIZE_0 0x00000000 /* Next Desc Size = 0 */ +#define NDSIZE_1 0x00010000 /* Next Desc Size = 1 */ +#define NDSIZE_2 0x00020000 /* Next Desc Size = 2 */ +#define NDSIZE_3 0x00030000 /* Next Desc Size = 3 */ +#define NDSIZE_4 0x00040000 /* Next Desc Size = 4 */ +#define NDSIZE_5 0x00050000 /* Next Desc Size = 5 */ +#define NDSIZE_6 0x00060000 /* Next Desc Size = 6 */ +#define NDSIZE 0x00070000 /* Next Desc Size */ +#define NDSIZE_OFFSET 16 /* Next Desc Size Offset */ +#define DMAFLOW_LIST 0x00004000 /* Desc List Mode */ +#define DMAFLOW_ARRAY 0x00005000 /* Desc Array Mode */ +#define DMAFLOW_LIST_DEMAND 0x00006000 /* Desc Demand List Mode */ +#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Desc Demand Array Mode */ +#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Run (DFETCH) */ +#define DMA_RUN 0x00000200 /* DMA Channel Run */ +#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Run (WAIT TRIG)*/ +#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Run (WAIT ACK) */ #else @@ -56,7 +56,7 @@ #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ #define DI_EN 0x0080 /* Data Interrupt Enable */ #define NDSIZE 0x0F00 /* Next Descriptor bitmask */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 */ #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ @@ -95,8 +95,8 @@ #define DMA_RUN_P 3 /* DMA Running Indicator */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ +#define CTYPE 0x0040 /* DMA Channel Type (Mem/Peri) */ +#define CTYPE_P 6 /* DMA Channel Type BIT POSITION */ #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/sdh.h b/arch/blackfin/include/asm/mach-common/bits/sdh.h index 3495558..1c60d4b 100644 --- a/arch/blackfin/include/asm/mach-common/bits/sdh.h +++ b/arch/blackfin/include/asm/mach-common/bits/sdh.h @@ -14,7 +14,7 @@ #define CMD_E 0x400 /* Command Enable */ #ifdef RSI_BLKSZ #define CMD_CRC_CHECK_D 0x800 /* CRC Check is disabled */ -#define CMD_DATA0_BUSY 0x1000 /* Check for Busy State on the DATA0 pin */ +#define CMD_DATA0_BUSY 0x1000 /* Check Busy State on DATA0 */ #endif /* Bit masks for SDH_PWR_CTL */ @@ -146,7 +146,7 @@ #define PWR_ON 0x600 /* Power On */ #define SD_CMD_OD 0x800 /* Open Drain Output */ #define BOOT_EN 0x1000 /* Boot Enable */ -#define BOOT_MODE 0x2000 /* Alternate Boot Mode */. +#define BOOT_MODE 0x2000 /* Alternate Boot Mode */ #define BOOT_ACK_EN 0x4000 /* Boot ACK is expected */ #endif diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 67996f4..cba18f4 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -181,7 +181,8 @@ void init_cplbtables(void) cplb_page_size = (16 * 1024 * 1024); cplb_page_mask = (~(cplb_page_size - 1)); #endif - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & cplb_page_mask)) { + while (i < 16 && extern_memory < + (CONFIG_SYS_MONITOR_BASE & cplb_page_mask)) { icplb_add(extern_memory, SDRAM_IGENERIC); dcplb_add(extern_memory, SDRAM_DGENERIC); extern_memory += cplb_page_size; diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c index 95cd519..97795e1 100644 --- a/arch/blackfin/lib/clocks.c +++ b/arch/blackfin/lib/clocks.c @@ -63,7 +63,8 @@ u_long get_cclk(void) /* Get the System clock */ #ifdef CGU_DIV -static u_long cached_sclk_pll_div, cached_sclk, cached_sclk0, cached_sclk1, cached_dclk; +static u_long cached_sclk_pll_div, cached_sclk; +static u_long cached_sclk0, cached_sclk1, cached_dclk; static u_long _get_sclk(u_long *cache) { u_long div, ssel; diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c index e0869c2..9d39ee0 100644 --- a/drivers/spi/bfin_spi6xx.c +++ b/drivers/spi/bfin_spi6xx.c @@ -101,34 +101,34 @@ void spi_init() } #define SPI_PINS(n) \ - [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 } + { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 } static unsigned short pins[][5] = { #ifdef SPI0_REGBASE - SPI_PINS(0), + [0] = SPI_PINS(0), #endif #ifdef SPI1_REGBASE - SPI_PINS(1), + [1] = SPI_PINS(1), #endif #ifdef SPI2_REGBASE - SPI_PINS(2), + [2] = SPI_PINS(2), #endif }; #define SPI_CS_PINS(n) \ - [n] = { \ + { \ P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \ P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \ P_SPI##n##_SSEL7, \ } static const unsigned short cs_pins[][7] = { #ifdef SPI0_REGBASE - SPI_CS_PINS(0), + [0] = SPI_CS_PINS(0), #endif #ifdef SPI1_REGBASE - SPI_CS_PINS(1), + [1] = SPI_CS_PINS(1), #endif #ifdef SPI2_REGBASE - SPI_CS_PINS(2), + [2] = SPI_CS_PINS(2), #endif }; diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index c408c22..010c8b6 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -80,10 +80,8 @@ /* * Network Settings */ -#define ADI_CMDS_NETWORK 1 #define CONFIG_NETCONSOLE 1 -#define CONFIG_NET_MULTI 1 -#define CONFIG_HOSTNAME bf609-ezkit +#define CONFIG_HOSTNAME "bf609-ezkit" #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_PORTS 1 #define CONFIG_DW_AUTONEG
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