Definition update and change from 16bit to 32bit
Signed-off-by: TsiChungLiew <[EMAIL PROTECTED]>
---
board/freescale/m5329evb/nand.c | 4 ++--
include/configs/M5329EVB.h | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index fefb42e..344a614 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -63,10 +63,10 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int
cmd)
nand_baseaddr |= CLR_ALE;
break;
case NAND_CTL_SETWP:
- fbcs->csmr2 |= CSMR_WP;
+ fbcs->csmr2 |= FBCS_CSMR_WP;
break;
case NAND_CTL_CLRWP:
- fbcs->csmr2 &= ~CSMR_WP;
+ fbcs->csmr2 &= ~FBCS_CSMR_WP;
break;
}
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 47d74a3..e956739 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -213,7 +213,7 @@
#ifdef NANDFLASH_SIZE
# define CFG_MAX_NAND_DEVICE 1
-# define CFG_NAND_BASE (CFG_CS2_BASE << 16)
+# define CFG_NAND_BASE CFG_CS2_BASE
# define CFG_NAND_SIZE 1
# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
# define NAND_MAX_CHIPS 1
@@ -224,7 +224,7 @@
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif
-#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
+#define CFG_FLASH_BASE CFG_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -254,12 +254,12 @@
#define CFG_CS0_MASK 0x007f0001
#define CFG_CS0_CTRL 0x00001fa0
-#define CFG_CS1_BASE 0x1000
+#define CFG_CS1_BASE 0x10000000
#define CFG_CS1_MASK 0x001f0001
#define CFG_CS1_CTRL 0x002A3780
#ifdef NANDFLASH_SIZE
-#define CFG_CS2_BASE 0x2000
+#define CFG_CS2_BASE 0x20000000
#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
#define CFG_CS2_CTRL 0x00001f60
#endif
--
1.5.2
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