Kim, The patch also cause the MPC8315ERDB broken, the 8315ERDB can not boot up.
The root cause is that the SATA clock is not correct. I will send one patch to fix it. Please merge it. Thanks, Dave > -----Original Message----- > From: [EMAIL PROTECTED] > [mailto:[EMAIL PROTECTED] On Behalf > Of Phillips Kim > Sent: 2008?1?16? 2:38 PM > To: u-boot-users@lists.sourceforge.net > Cc: D'Abbraccio Joe; Reiss Michael > Subject: [U-Boot-Users] [PATCH 1/2] mpc83xx: add support for > more system clock performance controls > > System registers that are modified are the Arbiter Configuration > Register (ACR), the System Priority Control Register (SPCR), and the > System Clock Configuration Register (SCCR). > > Signed-off by: Michael F. Reiss <[EMAIL PROTECTED]> > Signed-off by: Joe D'Abbraccio <[EMAIL PROTECTED]> > Signed-off-by: Kim Phillips <[EMAIL PROTECTED]> > --- > cpu/mpc83xx/cpu_init.c | 73 > +++++++++++++++++++++++++++++++++-------------- > cpu/mpc83xx/speed.c | 12 ++++---- > include/mpc83xx.h | 13 ++++++-- > 3 files changed, 67 insertions(+), 31 deletions(-) > > diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c > index 18d5a76..3337d8c 100644 > --- a/cpu/mpc83xx/cpu_init.c > +++ b/cpu/mpc83xx/cpu_init.c > @@ -78,59 +78,88 @@ void cpu_init_f (volatile immap_t * im) > im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | > (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT); > #endif > > +#ifdef CFG_ACR_RPTCNT > + /* Arbiter repeat count */ > + im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | > + (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT); > +#endif > + > +#ifdef CFG_SPCR_TSECEP > + /* all TSEC's Emergency priority */ > + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | > + (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT); > +#endif > + > #ifdef CFG_SPCR_TSEC1EP > /* TSEC1 Emergency priority */ > - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | > (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); > + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | > + (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); > #endif > > #ifdef CFG_SPCR_TSEC2EP > /* TSEC2 Emergency priority */ > - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | > (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); > + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | > + (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); > +#endif > + > +#ifdef CFG_SCCR_ENCCM > + /* Encryption clock mode */ > + im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | > + (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT); > +#endif > + > +#ifdef CFG_SCCR_PCICM > + /* PCI & DMA clock mode */ > + im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | > + (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT); > +#endif > + > +#ifdef CFG_SCCR_TSECCM > + /* all TSEC's clock mode */ > + im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) | > + (CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT); > #endif > > #ifdef CFG_SCCR_TSEC1CM > /* TSEC1 clock mode */ > - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | > (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); > + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | > + (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); > #endif > > #ifdef CFG_SCCR_TSEC2CM > - /* TSEC2 & I2C1 clock mode */ > - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | > (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); > + /* TSEC2 clock mode */ > + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | > + (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); > #endif > > #ifdef CFG_SCCR_TSEC1ON > /* TSEC1 clock switch */ > - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | > (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); > + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | > + (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); > #endif > > #ifdef CFG_SCCR_TSEC2ON > /* TSEC2 clock switch */ > - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | > (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); > + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | > + (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); > #endif > > #ifdef CFG_SCCR_USBMPHCM > /* USB MPH clock mode */ > - im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | > (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); > -#endif > - > -#ifdef CFG_SCCR_PCICM > - /* PCI & DMA clock mode */ > - im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | > (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT); > + im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | > + (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); > #endif > > #ifdef CFG_SCCR_USBDRCM > /* USB DR clock mode */ > - im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | > (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); > + im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | > + (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); > #endif > > -#ifdef CFG_SCCR_ENCCM > - /* Encryption clock mode */ > - im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | > (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT); > -#endif > - > -#ifdef CFG_ACR_RPTCNT > - /* Arbiter repeat count */ > - im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | > (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); > +#ifdef CFG_SCCR_SATACM > + /* SATA controller clock mode */ > + im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) | > + (CFG_SCCR_SATACM << SCCR_SATACM_SHIFT); > #endif > > /* RSR - Reset Status Register - clear all status (4.6.1.3) */ > diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c > index 4f5a866..61c9379 100644 > --- a/cpu/mpc83xx/speed.c > +++ b/cpu/mpc83xx/speed.c > @@ -367,21 +367,21 @@ int get_clocks(void) > #endif > > #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) > - switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { > - case 0: > + switch ((sccr & SCCR_SATACM) >> SCCR_SATACM_SHIFT) { > + case SCCR_SATACM_0: > sata_clk = 0; > break; > - case 1: > + case SCCR_SATACM_1: > sata_clk = csb_clk; > break; > - case 2: > + case SCCR_SATACM_2: > sata_clk = csb_clk / 2; > break; > - case 3: > + case SCCR_SATACM_3: > sata_clk = csb_clk / 3; > break; > default: > - /* unkown SCCR_SATA1CM value */ > + /* unkown SCCR_SATACM value */ > return -11; > } > #endif > diff --git a/include/mpc83xx.h b/include/mpc83xx.h > index 7299ca0..39cecf2 100644 > --- a/include/mpc83xx.h > +++ b/include/mpc83xx.h > @@ -725,13 +725,20 @@ > #define SCCR_USBCM_3 0x00F00000 > > #elif defined(CONFIG_MPC8313) > -/* TSEC1 bits are for TSEC2 as well */ > #define SCCR_TSEC1CM 0xc0000000 > #define SCCR_TSEC1CM_SHIFT 30 > +#define SCCR_TSEC1CM_0 0x00000000 > #define SCCR_TSEC1CM_1 0x40000000 > #define SCCR_TSEC1CM_2 0x80000000 > #define SCCR_TSEC1CM_3 0xC0000000 > > +#define SCCR_TSEC2CM 0x30000000 > +#define SCCR_TSEC2CM_SHIFT 28 > +#define SCCR_TSEC2CM_0 0x00000000 > +#define SCCR_TSEC2CM_1 0x10000000 > +#define SCCR_TSEC2CM_2 0x20000000 > +#define SCCR_TSEC2CM_3 0x30000000 > + > #define SCCR_TSEC1ON 0x20000000 > #define SCCR_TSEC1ON_SHIFT 29 > #define SCCR_TSEC2ON 0x10000000 > @@ -831,8 +838,6 @@ > #define SCCR_PCIEXP2CM_3 0x000c0000 > > /* All of the four SATA controllers must have the same clock ratio */ > -#define SCCR_SATA1CM 0x000000c0 > -#define SCCR_SATA1CM_SHIFT 6 > #define SCCR_SATACM 0x000000ff > #define SCCR_SATACM_SHIFT 0 > #define SCCR_SATACM_0 0x00000000 > @@ -852,6 +857,7 @@ > */ > #define CSCONFIG_EN 0x80000000 > #define CSCONFIG_AP 0x00800000 > +#define CSCONFIG_ODT_WR_ACS 0x00010000 > #define CSCONFIG_ROW_BIT 0x00000700 > #define CSCONFIG_ROW_BIT_12 0x00000000 > #define CSCONFIG_ROW_BIT_13 0x00000100 > @@ -1480,6 +1486,7 @@ > > /* DDRCDR - DDR Control Driver Register > */ > +#define DDRCDR_DHC_EN 0x80000000 > #define DDRCDR_EN 0x40000000 > #define DDRCDR_PZ 0x3C000000 > #define DDRCDR_PZ_MAXZ 0x00000000 > -- > 1.5.3 > > > -------------------------------------------------------------- > ----------- > This SF.net email is sponsored by: Microsoft > Defy all challenges. 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