* split the BAT initialization so that only 2 BATs (for the boot page
and stack) are programmed very early on. The rest are initialized later.
* Move other BAT setup, ccsrbar setup, and law setup later in the code
after translation has been enabled.
These changes will facilitate the moving of law and BAT initialization
to C code, and will aid with 36-bit physical addressing support.
Signed-off-by: Becky Bruce <[EMAIL PROTECTED]>
---
cpu/mpc86xx/start.S | 122 +++++++++++++++++++++++++++++----------------------
1 files changed, 69 insertions(+), 53 deletions(-)
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index c83310a..ba899f6 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -235,17 +235,8 @@ in_flash:
bl enable_ext_addr
/* setup the bats */
- bl setup_bats
- sync
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /* setup ccsrbar */
- bl setup_ccsrbar
-#endif
+ bl early_bats
- /* setup the law entries */
- bl law_entry
- sync
/*
* Cache must be enabled here for stack-in-cache trick.
* This means we need to enable the BATS.
@@ -282,6 +273,19 @@ in_flash:
GET_GOT /* initialize GOT access */
+ /* setup the rest of the bats */
+ bl setup_bats
+ bl clear_tlbs
+ sync
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /* setup ccsrbar */
+ bl setup_ccsrbar
+#endif
+
+ bl law_entry
+ sync
+
/* run low-level CPU init code (from Flash) */
bl cpu_init_f
sync
@@ -359,6 +363,7 @@ invalidate_bats:
/* setup_bats - set them up to some initial state */
+ /* Skip any BATS setup in early_bats */
.globl setup_bats
setup_bats:
@@ -454,42 +459,6 @@ setup_bats:
mtspr DBAT4U, r3
isync
- /* IBAT 5 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr IBAT5L, r4
- mtspr IBAT5U, r3
- isync
-
- /* DBAT 5 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr DBAT5L, r4
- mtspr DBAT5U, r3
- isync
-
- /* IBAT 6 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr IBAT6L, r4
- mtspr IBAT6U, r3
- isync
-
- /* DBAT 6 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr DBAT6L, r4
- mtspr DBAT6U, r3
- isync
-
/* IBAT 7 */
addis r4, r0, [EMAIL PROTECTED]
ori r4, r4, [EMAIL PROTECTED]
@@ -508,18 +477,65 @@ setup_bats:
mtspr DBAT7U, r3
isync
-1:
- addis r3, 0, 0x0000
- addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
+ sync
+ blr
+
+/*
+ * early_bats:
+ *
+ * Set up bats needed early on - this is usually the BAT for the
+ * stack-in-cache and the Flash
+ */
+ .globl early_bats
+early_bats:
+ /* IBAT 5 */
+ lis r4, [EMAIL PROTECTED]
+ ori r4, r4, [EMAIL PROTECTED]
+ lis r3, [EMAIL PROTECTED]
+ ori r3, r3, [EMAIL PROTECTED]
+ mtspr IBAT5L, r4
+ mtspr IBAT5U, r3
isync
+ /* DBAT 5 */
+ lis r4, [EMAIL PROTECTED]
+ ori r4, r4, [EMAIL PROTECTED]
+ lis r3, [EMAIL PROTECTED]
+ ori r3, r3, [EMAIL PROTECTED]
+ mtspr DBAT5L, r4
+ mtspr DBAT5U, r3
+ isync
+
+ /* IBAT 6 */
+ lis r4, [EMAIL PROTECTED]
+ ori r4, r4, [EMAIL PROTECTED]
+ lis r3, [EMAIL PROTECTED]
+ ori r3, r3, [EMAIL PROTECTED]
+ mtspr IBAT6L, r4
+ mtspr IBAT6U, r3
+ isync
+
+ /* DBAT 6 */
+ lis r4, [EMAIL PROTECTED]
+ ori r4, r4, [EMAIL PROTECTED]
+ lis r3, [EMAIL PROTECTED]
+ ori r3, r3, [EMAIL PROTECTED]
+ mtspr DBAT6L, r4
+ mtspr DBAT6U, r3
+ isync
+ blr
+
+ .globl clear_tlbs
+clear_tlbs:
+ addis r3, 0, 0x0000
+ addis r5, 0, 0x4
+ isync
tlblp:
- tlbie r3
+ tlbie r3
sync
- addi r3, r3, 0x1000
- cmp 0, 0, r3, r5
+ addi r3, r3, 0x1000
+ cmp 0, 0, r3, r5
blt tlblp
-
blr
.globl enable_addr_trans
--
1.5.3.7
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