Shinya Kuribayashi wrote:
>> I think that on my application the UNCACHED_SDRAM should map the address
>> on KSEG1 (how it is now) but this simply doesn't work. Instead, using
>> the PHYSADDR(a) macro... the kernel is able to start.
>>
>> I suspect that there are issues on cache management. Can be?
>
> IMHO it's not related to cache.
How do you set ERL and EXL bits? Please try to clear them at the
STATUS register initialization like:
reset:
<snip>
/* STATUS register */
mfc0 k0, CP0_STATUS
- li k1, ~ST0_IE
+ li k1, ~(ST0_ERL | ST0_EXL | ST0_IE)
and k0, k1
mtc0 k0, CP0_STATUS
ERL and EXL disable exceptions. Due to this spec, we are in danger
of overlooking something critical. If this change brings in new
exception(s), please fix the causes of them first. Hope this helps.
Shinya
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