In message <[EMAIL PROTECTED]> you wrote:
> For current SPARC architectures (LEON2 and LEON3) each read from the
> FLASH must lead to a cache miss. This is because FLASH can not be set
> non-cacheable since program code resides there, and alternatively disabling
> cache is poor from performance view, or doing a cache flush between each
> read
> is even poorer.
>
> Forcing a cache miss on a SPARC is done by a special instruction "lda" -
> load alternative space, the alternative space number (ASI) is processor
> implementation spcific and can be found by including <asm/processor.h>.
>
> SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address.
>
> Best Regards,
> Daniel Hellstrom
>
>
> drivers/mtd/cfi_flash.c | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
>
>
> diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
> index 439c950..6fc6bc4 100644
> --- a/drivers/mtd/cfi_flash.c
> +++ b/drivers/mtd/cfi_flash.c
> @@ -241,8 +241,12 @@ static u32 flash_read32(void *addr)
>
> static u64 flash_read64(void *addr)
> {
> +#ifdef CONFIG_SPARC
> + return __raw_readq(addr);
> +#else
> /* No architectures currently implement __raw_readq() */
> return *(volatile u64 *)addr;
> +#endif
> }
Instead of #ifdef'fing this code, you should implement a private
(SPARC specific) version of flash_read64() and probably make the
existing one "weak" so it can be overwritten by such custom
definitions.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED]
If I can have honesty, it's easier to overlook mistakes.
-- Kirk, "Space Seed", stardate 3141.9
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