Shinya Kuribayashi wrote:
>> But simply deleting it is definitely not a good idea, as it would most
>> probably break existing board support.
>
> I still think this removal will not break any existing targets, but yes
> agreed. I'll try to introduce a #ifdef alternative.
Patch attached. Any comments are still appreciated. Thanks.
================>
[MIPS] mips_cache_lock: Introduce CFG_INIT_RAM_LOCK
From: Shinya Kuribayashi <[EMAIL PROTECTED]>
We don't have to lock cache lines for stack use. Meanwhile, once U-Boot
locks cache, but never gets them unlocked. So the code relies on whatever
gets loaded after U-Boot to re-initialize the cache and clear the locks.
For these reasons, I proposed the removal of mips_cache_lock() from the
global start-up routines.
This patch makes mips_cache_lock() user-selectable so that we don't break
any existing board support. Let's see how things go for a while.
Signed-off-by: Shinya Kuribayashi <[EMAIL PROTECTED]>
---
cpu/mips/cache.S | 2 ++
cpu/mips/start.S | 2 ++
include/configs/dbau1x00.h | 1 +
include/configs/gth2.h | 1 +
include/configs/incaip.h | 1 +
include/configs/pb1x00.h | 1 +
include/configs/purple.h | 2 ++
include/configs/qemu-mips.h | 1 +
include/configs/tb0229.h | 1 +
9 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 443240e..ea921a0 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -238,6 +238,7 @@ dcache_disable:
.end dcache_disable
+#ifdef CFG_INIT_RAM_LOCK
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
@@ -263,3 +264,4 @@ mips_cache_lock:
j ra
.end mips_cache_lock
+#endif /* CFG_INIT_RAM_LOCK */
\ No newline at end of file
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index c92b162..901e3ef 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -267,10 +267,12 @@ reset:
/* Set up temporary stack.
*/
+#ifdef CFG_INIT_RAM_LOCK
li a0, CFG_INIT_SP_OFFSET
la t9, mips_cache_lock
jalr t9
nop
+#endif
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0)
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index b2f606f..5dfe7b3 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -187,6 +187,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10)
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_SP_OFFSET 0x400000
/* We boot from this flash, selected with dip switch */
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index c2a50c1..a50e212 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -141,6 +141,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10)
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_SP_OFFSET 0x400000
/* We boot from this flash, selected with dip switch */
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 5ca00b3..2528b35 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -140,6 +140,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10)
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_SP_OFFSET 0x400000
#define CFG_FLASH_BASE PHYS_FLASH_1
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 810e0f0..e3a38f8 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -105,6 +105,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10)
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_SP_OFFSET 0x4000000
/* We boot from this flash, selected with dip switch */
diff --git a/include/configs/purple.h b/include/configs/purple.h
index 1be4e05..f936f59 100644
--- a/include/configs/purple.h
+++ b/include/configs/purple.h
@@ -101,6 +101,8 @@
#define CFG_SDRAM_BASE 0x80000000
+#define CFG_INIT_RAM_LOCK 1
+
#define CFG_INIT_SP_OFFSET 0x400000
#define CFG_MALLOC_LEN 128*1024
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index e164019..5371e32 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -142,6 +142,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10)
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_SP_OFFSET 0x400000
/* We boot from this flash, selected with dip switch */
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
index dadf5d3..61495a7 100644
--- a/include/configs/tb0229.h
+++ b/include/configs/tb0229.h
@@ -143,6 +143,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10)
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_SP_OFFSET 0x400000
#define CFG_FLASH_BASE PHYS_FLASH_1
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