This affects EBC_BXCR_BW_32BIT defined in include/ppc440.h According to the AMCC 440EPx User Manual (v1.14), pg 591, figure 22-18, BW (bits 17:18) should be 10 for a 32-bit bus width. This is also repeated for the NAND controller, section 23.4.5 on pg 600.
According to the IBM 440GX User's Manual (November 21, 2003), pg 1037, figure 30-23, BW (bits 17:18) should be 11. A rather old manual. Can others help confirm the settings for these processors and other 440 family members. Thanks. -- Andrew E. Mileski ------------------------------------------------------------------------- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone _______________________________________________ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
