On Tue, Apr 29, 2008 at 12:18 PM, Andre Schwarz <[EMAIL PROTECTED]> wrote: > The Vitesse VSC8601 RGMII PHY has internal delay for both Rx > and Tx clock lines. They are configured using 2 bits in extended > register 0x17. > Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have > been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay. > > Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
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