Dear Jon, in message <[EMAIL PROTECTED]> Travis Wheatley wrote: > > The 7610 and related parts have an L2IP bit in the L2CR that is > monitored to signal when the L2 cache invalidate is complete whereas the > 7450 and related parts utilize L2I for this purpose. However, the > current code does not account for this difference. Additionally the 86xx > L2 cache invalidate code used an "andi" instruction where an "andis" > instruction should have been used. > > This patch addresses both of these bugs.
Will you please ACK this patch? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] When the ax entered the forest, the trees said, "The handle is one of us!" -- Turkish proverb ------------------------------------------------------------------------- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone _______________________________________________ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
