On 17:14 Sat 03 May , Martha J Marx wrote:
> Configuration changes added to support ADS5121 Rev 3 version of the board.
> This includes changes to the ref clock, memory size (from 256 to 512), the
> addition of PCI functionality and Makefile options to build either the Rev 3
> or Rev 2 U-Boot. The new README explains these options.
>
>
> Signed-off-by: Martha J Marx <[EMAIL PROTECTED]>
same as previous patch
plus some coding style issue
pLease fix and resubmit
Best Regards,
J.
> +++ b/board/ads5121/README
> @@ -0,0 +1,9 @@
> +To configure for the Rev 3.x ADS5121 type
> +make ads5121_config
> +This will automatically include PCI and the Real Time CLock abilities,
> +and set the correct frequency and memory configuration.
> +
> +To configure for the Rev 2 ADS5121 type
> +make ads5121_256_config
> +
> +
> diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
> index 8629b03..35544f1 100644
> --- a/board/ads5121/ads5121.c
> +++ b/board/ads5121/ads5121.c
> @@ -26,7 +26,9 @@
> #include <asm/bitops.h>
> #include <command.h>
> #include <fdt_support.h>
> -
> +#ifdef CONFIG_MISC_INIT_R
> +#include <i2c.h>
> +#endif
> /* Clocks in use */
> #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |
> \
> CLOCK_SCCR1_LPC_EN | \
> @@ -50,7 +52,6 @@ int board_early_init_f (void)
> {
> volatile immap_t *im = (immap_t *) CFG_IMMR;
> u32 lpcaw;
> -
do not remove please
> /*
> * Initialize Local Window for the CPLD registers access (CS2
> selects
> * the CPLD chip)
> @@ -58,7 +59,6 @@ int board_early_init_f (void)
> im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
> CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
> im->lpc.cs_cfg[2] = CFG_CS2_CFG;
> -
> /*
> * According to MPC5121e RM, configuring local access windows should
> * be followed by a dummy read of the config register that was
> @@ -73,8 +73,22 @@ int board_early_init_f (void)
> * Without this the flash identification routine fails, as it needs
> to issue
> * write commands in order to establish the device ID.
> */
> - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
>
> +#ifdef CONFIG_ADS5121_256
> + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
> +#else
> + if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
> +
please remove empty line
> + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
> + } else {
> + /* running from Backup flash */
> + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
> + }
> +#endif
> + /*
> + * Configure Flash Speed
> + */
> + *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) =
> CFG_CS0_CFG;
> /*
> * Enable clocks
> */
> @@ -203,6 +217,18 @@ int checkboard (void)
> reg[i] |= 0x00000003;
> return 0;
> }
> +#ifdef CONFIG_MISC_INIT_R
> +int misc_init_r(void)
> +{
> + /*
> + * I2C writes to turn on DVI
> + */
> + static uchar buf[1] = {0xbf};
^
whitespace
add an empty line
> + i2c_set_bus_num(2);
> + i2c_write(0x38, 0x8, 1, buf, 1);
> + return 0;
> +}
> +#endif
>
> #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> void ft_board_setup(void *blob, bd_t *bd)
> diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c
> index bed77ac..3b45bfe 100644
> --- a/cpu/mpc512x/cpu.c
> +++ b/cpu/mpc512x/cpu.c
> @@ -133,8 +133,9 @@ void watchdog_reset (void)
-------------------------------------------------------------------------
This SF.net email is sponsored by the 2008 JavaOne(SM) Conference
Don't miss this year's exciting event. There's still time to save $100.
Use priority code J8TL2D2.
http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone
_______________________________________________
U-Boot-Users mailing list
U-Boot-Users@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/u-boot-users
