The Atmel boards can handle 8 or 16 bit NAND memories. This patch
makes the support configurable in the board config header file
(CFG_NAND_DBW_8 or CFG_NAND_DBW_16).
Signed-off-by: Stelian Pop <[EMAIL PROTECTED]>
---
board/atmel/at91cap9adk/at91cap9adk.c | 10 +++++++---
board/atmel/at91cap9adk/nand.c | 3 +++
include/configs/at91cap9adk.h | 1 +
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/board/atmel/at91cap9adk/at91cap9adk.c
b/board/atmel/at91cap9adk/at91cap9adk.c
index 310a3ef..67e16bb 100644
--- a/board/atmel/at91cap9adk/at91cap9adk.c
+++ b/board/atmel/at91cap9adk/at91cap9adk.c
@@ -25,7 +25,7 @@
#include <common.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91cap9_matrix.h>
-#include <asm/arch/at91sam_smc.h>
+#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
@@ -116,7 +116,12 @@ static void at91cap9_nand_hw_init(void)
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
- AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
+#ifdef CFG_NAND_DBW_16
+ AT91_SMC_DBW_16 |
+#else /* CFG_NAND_DBW_8 */
+ AT91_SMC_DBW_8 |
+#endif
+ AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
@@ -252,7 +257,6 @@ int board_init(void)
#ifdef CONFIG_USB_OHCI_NEW
at91cap9_uhp_hw_init();
#endif
-
return 0;
}
diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c
index 28091a4..0432ef1 100644
--- a/board/atmel/at91cap9adk/nand.c
+++ b/board/atmel/at91cap9adk/nand.c
@@ -63,6 +63,9 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd,
int cmd)
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
+#ifdef CFG_NAND_DBW_16
+ nand->options = NAND_BUSWIDTH_16;
+#endif
nand->hwcontrol = at91cap9adk_nand_hwcontrol;
nand->chip_delay = 20;
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index c891fa8..7887b36 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -110,6 +110,7 @@
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
+#define CFG_NAND_DBW_8 1
/* Ethernet */
#define CONFIG_MACB 1
--
1.5.3.3
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