---
board/cta5000s/Makefile | 50 ++++
board/cta5000s/config.mk | 30 +++
board/cta5000s/cta5000s.c | 565 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 645 insertions(+), 0 deletions(-)
create mode 100644 board/cta5000s/Makefile
create mode 100644 board/cta5000s/config.mk
create mode 100644 board/cta5000s/cta5000s.c
diff --git a/board/cta5000s/Makefile b/board/cta5000s/Makefile
new file mode 100644
index 0000000..be7e213
--- /dev/null
+++ b/board/cta5000s/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cta5000s/config.mk b/board/cta5000s/config.mk
new file mode 100644
index 0000000..5fca8c7
--- /dev/null
+++ b/board/cta5000s/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd. <[EMAIL PROTECTED]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Rattler series boards by Analogue & Micro
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/cta5000s/cta5000s.c b/board/cta5000s/cta5000s.c
new file mode 100644
index 0000000..70204f8
--- /dev/null
+++ b/board/cta5000s/cta5000s.c
@@ -0,0 +1,565 @@
+/*
+ * Aztek Networks CTA5000S board u-boot board support
+ *
+ * Copyright 2007 Aztek Networks, Inc.
+ *
+ * Authors: Scott Mann <[EMAIL PROTECTED]>
+ * jblack <[EMAIL PROTECTED]>
+ *
+ * Based on: U-Boot configuration for Analogue&Micro Rattler boards.
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+#include <ioports.h>
+#include <configs/cta5000s.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+/*
+ * See include/configs/cta5000s.h for CFG_* settings
+ * All values in the following tables taken from
+ * chapter 6 of the cta Programmer's Guide
+ */
+
+/* table is used by cpu/mpc8260/cpu_init.c */
+const iop_conf_t iop_conf_tab[4][32] = {
+ /* Port A */
+ {/*conf ppar, psor, pdir, podr, pdat */
+ /* PA31 */ {CFG_FCC1, 1, 1, 0, 0, 0},
+ /* FCC1 MII COL */
+ /* PA30 */ {CFG_FCC1, 1, 1, 0, 0, 0},
+ /* FCC1 MII CRS */
+ /* PA29 */ {CFG_FCC1, 1, 1, 1, 0, 0},
+ /* FCC1 MII TX_ER */
+ /* PA28 */ {CFG_FCC1, 1, 1, 1, 0, 0},
+ /* FCC1 MII TX_EN */
+ /* PA27 */ {CFG_FCC1, 1, 1, 0, 0, 0},
+ /* FCC1 MII RX_DV */
+ /* PA26 */ {CFG_FCC1, 1, 1, 0, 0, 0},
+ /* FCC1 MII RX_ER */
+ /* PA25 */ {CFG_AZ_RY_BY, 0, 0, 0, 0, 0},
+ /* Rdy/Bsy flash */
+ /* PA24 */ {CFG_AZ_FPGA, 0, 0, 0, 1, 1},
+ /* FPGAINIT */
+ /* PA23 */ {CFG_AZ_FPGA, 0, 0, 1, 0, 1},
+ /* FPGAPROGRW */
+ /* PA22 */ {CFG_AZ_FPGA, 0, 0, 1, 0, 1},
+ /* FPGAPGM */
+ /* PA21 */ {CFG_FCC1, 1, 0, 1, 0, 0},
+ /* FCC1 MII TxD[3] */
+ /* PA20 */ {CFG_FCC1, 1, 0, 1, 0, 0},
+ /* FCC1 MII TxD[2] */
+ /* PA19 */ {CFG_FCC1, 1, 0, 1, 0, 0},
+ /* FCC1 MII TxD[1] */
+ /* PA18 */ {CFG_FCC1, 1, 0, 1, 0, 0},
+ /* FCC1 MII TxD[0] */
+ /* PA17 */ {CFG_FCC1, 1, 0, 0, 0, 0},
+ /* FCC1 MII RxD[0] */
+ /* PA16 */ {CFG_FCC1, 1, 0, 0, 0, 0},
+ /* FCC1 MII RxD[1] */
+ /* PA15 */ {CFG_FCC1, 1, 0, 0, 0, 0},
+ /* FCC1 MII RxD[2] */
+ /* PA14 */ {CFG_FCC1, 1, 0, 0, 0, 0},
+ /* FCC1 MII RxD[3] */
+ /* PA13 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0},
+ /* PLLTIECLR */
+ /* PA12 */ {CFG_AZ_PLL, 0, 0, 1, 0, 1},
+ /* PLLSEL1 */
+ /* PA11 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0},
+ /* PLLSEL0 */
+ /* PA10 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0},
+ /* PLLTIEEN */
+ /* PA9 */ {CFG_AZ_FAN, 1, 0, 0, 0, 0},
+ /* FAN GOOD */
+ /* PA8 */ {CFG_AZ_FAN, 1, 0, 1, 0, 0},
+ /* FAN OFF */
+ /* PA7 */ {CFG_AZ_CF, 0, 0, 0, 0, 0},
+ /* CF car detect 1 */
+ /* PA6 */ {CFG_AZ_CF, 0, 0, 0, 0, 0},
+ /* CF car detect 2 */
+ /* PA5 */ {CFG_AZ_EXALM, 0, 0, 0, 0, 0},
+ /* Ext Alarm 0 */
+ /* PA4 */ {CFG_AZ_EXALM, 0, 0, 0, 0, 0},
+ /* Ext Alarm 1 */
+ /* PA3 */ {CFG_AZ_MCC2, 1, 0, 0, 0, 0},
+ /* CLK19 for MCC2 */
+ /* PA2 */ {CFG_AZ_MCC2, 1, 0, 0, 0, 0},
+ /* CLK20 for MCC2 */
+ /* PA1 */ {CFG_AZ_FPGA, 0, 0, 0, 0, 0},
+ /* FPGA busy */
+ /* PA0 */ {CFG_AZ_FPGA, 0, 0, 0, 0, 0}
+ /* FPGA done */
+ },
+ /* Port B */
+ {/*conf ppar, psor, pdir, podr, pdat */
+ /* PB31 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 TXDB2 */
+ /* PB30 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 RXDB2 */
+ /* PB29 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 RSYNCB2 */
+ /* PB28 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 TSYNCB2 */
+ /* PB27 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 TXDC2 */
+ /* PB26 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 RXDC2 */
+ /* PB25 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 TSYNCC2 */
+ /* PB24 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 RSYNCC2 */
+ /* PB23 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 TXDD2 */
+ /* PB22 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 RXDD2 */
+ /* PB21 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 TSYNCD2 */
+ /* PB20 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 RSYNCD2 */
+ /* PB19 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0},
+ /* PLL RESET */
+ /* PB18 */ {CFG_AZ_PLL, 0, 0, 0, 0, 0},
+ /* PLL LOCK input */
+ /* PB17 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* CLK17 MCC2 */
+ /* PB16 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* CLK18 MCC2 */
+ /* PB15 */ {CFG_AZ_SCC2, 1, 0, 0, 0, 0},
+ /* SCC2 RXD */
+ /* PB14 */ {CFG_AZ_SCC3, 1, 0, 0, 0, 0},
+ /* SCC3 RXD */
+ /* PB13 */ {CFG_AZ_PLL, 0, 0, 0, 0, 0},
+ /* PLL Normal input */
+ /* PB12 */ {CFG_AZ_SCC2, 1, 1, 1, 0, 0},
+ /* SCC2 TXD */
+ /* PB11 */ {CFG_AZ_PLL, 0, 0, 0, 0, 0},
+ /* PLL Holdover */
+ /* PB10 */ {CFG_AZ_PLL, 0, 0, 0, 0, 0},
+ /* PLL Free run */
+ /* PB9 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0},
+ /* PLL Fast Lock */
+ /* PB8 */ {CFG_AZ_SCC3, 1, 0, 1, 0, 0},
+ /* SCC3 TXD */
+ /* PB7 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 TXDA2 */
+ /* PB6 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 RXDA2 */
+ /* PB5 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 TSYNCA2 */
+ /* PB4 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0},
+ /* MCC2 L1 RSYNCA2 */
+ /* PB3 */ {CFG_AZ_NA, 0, 0, 0, 0, 0},
+ /* not available */
+ /* PB2 */ {CFG_AZ_NA, 0, 0, 0, 0, 0},
+ /* not available */
+ /* PB1 */ {CFG_AZ_NA, 0, 0, 0, 0, 0},
+ /* not available */
+ /* PB0 */ {CFG_AZ_NA, 0, 0, 0, 0, 0}
+ /* not available */
+ },
+ /* Port C */
+ {/*conf ppar, psor, pdir, podr, pdat */
+ /* PC31 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC30 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC29 */ {CFG_AZ_SCC2, 1, 0, 0, 0, 0},
+ /* CLK3 SCC2 */
+ /* PC28 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC27 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC26 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC25 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC24 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC23 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC22 */ {CFG_FCC1, 1, 0, 0, 0, 0},
+ /* TxClk(CLK10) */
+ /* PC21 */ {CFG_FCC1, 1, 0, 0, 0, 0},
+ /* RxClk(CLK11) */
+ /* PC20 */ {CFG_AZ_SCC2, 1, 0, 0, 0, 0},
+ /* CLK12 SCC2 */
+ /* PC19 */ {CFG_AZ_MCC2, 1, 0, 0, 0, 0},
+ /* CLK13 MCC2 */
+ /* PC18 */ {CFG_AZ_MCC2, 1, 0, 0, 0, 0},
+ /* TxClk (CLK14) */
+ /* PC17 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC16 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC15 */ {CFG_AZ_SCC1, 0, 0, 0, 0, 0},
+ /* CTS for SCC1 */
+ /* PC14 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC13 */ {CFG_AZ_FAN, 0, 0, 0, 0, 0},
+ /* FAN present */
+ /* PC12 */ {CFG_AZ_ESA, 0, 0, 0, 0, 0},
+ /* ESA Relay good */
+ /* PC11 */ {CFG_AZ_SCC3, 0, 0, 0, 0, 0},
+ /* CTS for SCC3 */
+ /* PC10 */ {CFG_AZ_SCC3, 0, 0, 0, 0, 0},
+ /* CD for SCC3 */
+ /* PC9 */ {CFG_AZ_SCC3, 0, 0, 0, 0, 0},
+ /* CI for SCC3 */
+ /* PC8 */ {CFG_AZ_SCC3, 0, 0, 0, 0, 0},
+ /* DSR for SCC3 */
+ /* PC7 */ {CFG_AZ_MDM, 0, 0, 1, 0, 0},
+ /* MDM Reset */
+ /* PC6 */ {CFG_AZ_MDM, 0, 0, 1, 0, 1},
+ /* MDM CTR */
+ /* PC5 */ {CFG_AZ_FAN, 0, 0, 1, 0, 1},
+ /* FAN EE CS */
+ /* PC4 */ {CFG_AZ_ESA, 1, 0, 0, 0, 0},
+ /* ESA On */
+ /* PC3 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PC2 */ {CFG_AZ_ADC, 0, 0, 0, 0, 1},
+ /* ADC EOC IRQ */
+ /* PC1 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0},
+ /* PLL MSEL1 */
+ /* PC0 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0},
+ /* PLL MSEL0 */
+ },
+
+ /* Port D */
+ {/*conf ppar, psor, pdir, podr, pdat */
+ /* PD31 */ {CFG_AZ_SCC1, 1, 0, 0, 0, 0},
+ /* SCC1 RxD */
+ /* PD30 */ {CFG_AZ_SCC1, 1, 1, 1, 0, 0},
+ /* SCC1 TxD */
+ /* PD29 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* SCC1 RTS not used */
+ /* PD28 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD27 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD26 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD25 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD24 */ {CFG_AZ_MEZZ, 0, 0, 0, 0, 0},
+ /* Mezz present */
+ /* PD23 */ {CFG_AZ_SCC3, 0, 0, 1, 0, 1},
+ /* RTS SCC3 */
+ /* PD22 */ {CFG_AZ_TSI, 0, 0, 1, 0, 0},
+ /* TSI reset */
+ /* PD21 */ {CFG_AZ_BP, 0, 0, 1, 0, 1},
+ /* BP EE CS */
+ /* PD20 */ {CFG_AZ_ADC, 0, 0, 1, 0, 1},
+ /* ADC SEL */
+ /* PD19 */ {CFG_AZ_UN, 0, 0, 1, 0, 1},
+ /* unused */
+ /* PD18 */ {CFG_AZ_SPI, 1, 1, 0, 0, 0},
+ /* SPI CLK */
+ /* PD17 */ {CFG_AZ_SPI, 1, 1, 0, 0, 0},
+ /* SPI MOSI */
+ /* PD16 */ {CFG_AZ_SPI, 1, 1, 0, 0, 0},
+ /* SPI MISO */
+ /* PD15 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD14 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD13 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD12 */ {CFG_AZ_UN, 0, 0, 1, 0, 1},
+ /* unused */
+ /* PD11 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD10 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD9 */ {CFG_AZ_SMC1, 1, 0, 1, 0, 0},
+ /* SMC1 TXD */
+ /* PD8 */ {CFG_AZ_SMC1, 1, 0, 0, 0, 0},
+ /* SMC1 RXD */
+ /* PD7 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD6 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD5 */ {CFG_AZ_UN, 0, 0, 1, 0, 0},
+ /* unused */
+ /* PD4 */ {CFG_AZ_FPGA, 0, 0, 1, 0, 1},
+ /* FPGA PGMCS */
+ /* PD3 */ {CFG_AZ_NA, 0, 0, 0, 0, 0},
+ /* not available */
+ /* PD2 */ {CFG_AZ_NA, 0, 0, 0, 0, 0},
+ /* not available */
+ /* PD1 */ {CFG_AZ_NA, 0, 0, 0, 0, 0},
+ /* not available */
+ /* PD0 */ {CFG_AZ_NA, 0, 0, 0, 0, 0}
+ /* not available */
+ }
+};
+
+uint cta_upm_table[] = {
+
+ /* Read single-beat (RSS) 0x00 */
+ CTA_UPM_READ_CYCLE_RAM_WORD_0,
+ CTA_UPM_READ_CYCLE_RAM_WORD_1,
+ CTA_UPM_READ_CYCLE_RAM_WORD_2,
+ CTA_UPM_READ_CYCLE_RAM_WORD_3,
+ CTA_UPM_READ_CYCLE_RAM_WORD_4,
+ CTA_UPM_READ_CYCLE_RAM_WORD_5,
+ CTA_UPM_READ_CYCLE_RAM_WORD_6,
+ CTA_UPM_READ_CYCLE_RAM_WORD_7,
+
+ /* Read burst (RBS) 0x08 */
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+
+ /* 0x10 */
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+
+ /* Write single-beat (WSS) 0x18 */
+ CTA_UPM_WRITE_CYCLE_RAM_WORD_0,
+ CTA_UPM_WRITE_CYCLE_RAM_WORD_1,
+ CTA_UPM_WRITE_CYCLE_RAM_WORD_2,
+ CTA_UPM_WRITE_CYCLE_RAM_WORD_3,
+ CTA_UPM_WRITE_CYCLE_RAM_WORD_4,
+ CTA_UPM_WRITE_CYCLE_RAM_WORD_5,
+ CTA_UPM_WRITE_CYCLE_RAM_WORD_6,
+ UNUSED,
+
+ /* Write burst (WBS) 0x20 */
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+
+ /* Refresh timer (PTS) 0x30 */
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED,
+
+ /* Exception condition (EXS) 0x3C */
+ UNUSED,
+ UNUSED,
+ UNUSED,
+ UNUSED
+};
+
+long int initdram (int board_type)
+{
+ long int msize = CFG_SDRAM_SIZE;
+
+#ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ vu_char *ramaddr = (vu_char *) CFG_SDRAM_BASE;
+ uchar c = 0xFF;
+ uint psdmr = CFG_PSDMR;
+ int i;
+
+ immap->im_siu_conf.sc_ppc_acr = CFG_PPC_ACR;
+ immap->im_siu_conf.sc_ppc_alrh = CFG_PPC_ALRH;
+ immap->im_siu_conf.sc_tescr1 = CFG_TESCR1;
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ /* Initialise 60x bus SDRAM */
+ memctl->memc_psrt = CFG_PSRT;
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+ /* Precharge all banks */
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+ *ramaddr = c;
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+ for (i = 0; i < 8; i++) {
+ *ramaddr = c;
+ }
+ /* Mode Register write */
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+ *ramaddr = c;
+ memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
+ *ramaddr = c;
+#endif /* !CFG_RAMBOOT */
+
+ /* Return total 60x bus SDRAM size */
+ return msize * 1024 * 1024;
+}
+
+int board_early_init_f (void)
+{
+
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ uint table_size = sizeof (cta_upm_table) / sizeof (cta_upm_table[0]);
+
+ /* Aztek CTA clock configuration settings */
+ immap->im_siu_conf.sc_sypcr = CFG_SYPCR;
+ immap->im_siu_conf.sc_swsr = CFG_SWSR;
+ immap->im_siu_conf.sc_ppc_acr = (unsigned char)CFG_PPC_ACR;
+ immap->im_siu_conf.sc_ppc_alrh = CFG_PPC_ALRH;
+ immap->im_siu_conf.sc_ppc_alrl = CFG_PPC_ALRL;
+ immap->im_siu_conf.sc_lcl_acr = (unsigned char)CFG_LCL_ACR;
+ immap->im_siu_conf.sc_lcl_alrh = CFG_LCL_ALRH;
+ immap->im_siu_conf.sc_lcl_alrl = CFG_LCL_ALRL;
+ immap->im_siu_conf.sc_tescr1 = CFG_TESCR1;
+ immap->im_siu_conf.sc_tescr2 = CFG_TESCR2;
+ immap->im_siu_conf.sc_ltescr1 = CFG_LTESCR1;
+ immap->im_siu_conf.sc_ltescr2 = CFG_LTESCR2;
+ immap->im_siu_conf.sc_pdtea = CFG_PDTEA;
+ immap->im_siu_conf.sc_pdtem = (unsigned char)CFG_PDTEM;
+ immap->im_siu_conf.sc_ldtea = CFG_LDTEA;
+ immap->im_siu_conf.sc_ldtem = (unsigned char)CFG_LDTEM;
+
+ /* Aztek additional memory controller/upm settings */
+ memctl->memc_mamr = CFG_CTA_MAMR_PRELIM;
+ memctl->memc_mbmr = CFG_CTA_MBMR_PRELIM;
+ memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_psdmr = CFG_PSDMR;
+ memctl->memc_psrt = CFG_PSRT;
+ memctl->memc_lsdmr = CFG_LSDMR;
+ memctl->memc_lsrt = CFG_LSRT;
+
+ upmconfig (UPMA, cta_upm_table, table_size);
+ upmconfig (UPMB, cta_upm_table, table_size);
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ /* the fpga status pins on PORT A GPIO register */
+ uint status = 0;
+ uint *fpgaStatus = (uint *) 0xf0010d10;
+ int i = 140;
+
+ /* wait 140ms until the fpga is ready */
+ do {
+ if (!(FPGA_BUSY & *fpgaStatus)) {
+ i--;
+ udelay(1000);
+ }
+ if (i == 0)
+ break;
+
+ status = (FPGA_DONE & *fpgaStatus);
+ } while (status == 0);
+
+ uchar *fpgaVersion = (uchar *) 0x2002001f;
+
+ printf ("Manuf: Aztek Networks, Inc.\n");
+ printf ("Board: CTA5000S\n");
+
+ if (i == 0)
+ printf ("FPGA: did not initialize\n");
+ else
+ printf ("FPGA: %d \n", *fpgaVersion);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update (void *blob, bd_t * bd)
+{
+ int ret;
+
+ ret = fdt_fixup_memory (blob,
+ (u64) bd->bi_memstart, (u64) bd->bi_memsize);
+
+ if (ret < 0) {
+ printf ("ft_blob_update): cannot set /memory/reg "
+ "property err:%s\n", fdt_strerror (ret));
+ }
+}
+
+void ft_board_setup (void *blob, bd_t * bd)
+{
+ ft_cpu_setup (blob, bd);
+ ft_blob_update (blob, bd);
+}
+#endif
+/* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+#if defined (CONFIG_STATUS_LED)
+int misc_init_r (void)
+{
+ __led_init (0, 0);
+ return 0;
+}
+
+void __led_toggle (led_id_t _msk)
+{
+ *((uchar *) (CFG_LED_BASE)) ^= (0x30);
+}
+
+void __led_init (led_id_t _msk, int st)
+{
+ *((uchar *) (CFG_LED_BASE)) = 0x20;
+}
+
+void __led_set (led_id_t _msk, int _st)
+{
+ if ((_st == STATUS_LED_ON))
+ *((uchar *) (CFG_LED_BASE)) |= 0x10;
+ else
+ *((uchar *) (CFG_LED_BASE)) &= ~(0x10);
+}
+#endif
--
1.5.5.1
-------------------------------------------------------------------------
This SF.net email is sponsored by: Microsoft
Defy all challenges. Microsoft(R) Visual Studio 2008.
http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/
_______________________________________________
U-Boot-Users mailing list
U-Boot-Users@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/u-boot-users
