This patch adds support for OMAP3 platforms. This is mainly to setup the
infrastructure. ARMV7 requires a different I/D cache cleanup code which is
introduced in this patch.
Thanks to Laurent in pointing out the Cortex-A8 D-Cache issue with my first rev
patch.
Signed-off-by: Nishanth Menon<[EMAIL PROTECTED]>
---
arch/arm/Kconfig | 24 ++++++++++++++++++++
arch/arm/Makefile | 6 +++++
arch/arm/cpu/Makefile | 1
arch/arm/cpu/start-arm.S | 54 +++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 84 insertions(+), 1 deletion(-)
Index: u-boot-v2.git/arch/arm/Kconfig
===================================================================
--- u-boot-v2.git.orig/arch/arm/Kconfig 2008-05-20 18:20:54.000000000 -0500
+++ u-boot-v2.git/arch/arm/Kconfig 2008-05-21 10:41:17.000000000 -0500
@@ -47,6 +47,9 @@
config ARM926EJS
bool
+config ARMCORTEXA8
+ bool
+
# i.MX1, i.MXL, i.MX27 and i.MX31 are quite similar and thus
# handled in one arch
config ARCH_IMX
@@ -74,6 +77,10 @@
bool
select ARM926EJS
+config ARCH_OMAP
+ bool
+# ARM versions used varies on based on OMAP versions
+
choice
prompt "Select your board"
@@ -135,6 +142,13 @@
Say Y here if your are using Phytec's phyCORE-i.MX31 (pcm037) equipped
with a Freescale i.MX31 Processor
+config MACH_OMAP
+ bool "Texas Instruments' OMAP based platforms"
+ select ARCH_OMAP
+ select MACH_CAN_MODIFY_MALLOC_START
+ help
+ Say Y if you are using Texas Instrument's OMAP based platforms
+
endchoice
config IMX_CLKO
@@ -144,8 +158,9 @@
The i.MX SoCs have a Pin which can output different reference
frequencies.
Say y here if you want to have the clko command which lets you select
the
frequency to output on this pin.
-
+
source arch/arm/mach-netx/Kconfig
+source arch/arm/mach-omap/Kconfig
menu "Arm specific settings "
@@ -190,6 +205,13 @@
Provide the alternate malloc start address. Remember that the area
that will be used will be (this address) to (this address -
CFG_MALLOC_LEN - CONFIG_STACKSIZE)
+config ARMCORTEXA8_DCACHE_SKIP
+ bool "Skip DCache Invlidate"
+ depends on ARMCORTEXA8
+ default n
+ help
+ If your architecture configuration uses some other method of
disabling caches, enable this
+ So that the D-Cache invalidation logic is skipped
endmenu
source common/Kconfig
Index: u-boot-v2.git/arch/arm/Makefile
===================================================================
--- u-boot-v2.git.orig/arch/arm/Makefile 2008-05-20 18:20:54.000000000
-0500
+++ u-boot-v2.git/arch/arm/Makefile 2008-05-20 18:20:54.000000000 -0500
@@ -6,6 +6,7 @@
machine-$(CONFIG_ARCH_IMX) := imx
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
+machine-$(CONFIG_ARCH_OMAP) := omap
board-$(CONFIG_MACH_MX1ADS) := mx1ads
board-$(CONFIG_MACH_ECO920) := eco920
board-$(CONFIG_MACH_SCB9328) := scb9328
@@ -13,6 +14,7 @@
board-$(CONFIG_MACH_IMX27ADS) := imx27ads
board-$(CONFIG_MACH_NXDB500) := netx
board-$(CONFIG_MACH_PCM037) := pcm037
+board-$(CONFIG_MACH_OMAP) := omap
# FIXME "cpu-y" never used on ARM!
cpu-$(CONFIG_ARM920T) := arm920t
cpu-$(CONFIG_ARM926EJS) := arm926ejs
@@ -22,6 +24,10 @@
CPPFLAGS += -mabi=apcs-gnu -DTEXT_BASE=$(TEXT_BASE) -P
CFLAGS += -Os
+# Add architecture specific flags
+ifeq ($(CONFIG_ARMCORTEXA8),y)
+CPPFLAGS += -march=armv7a
+endif
# Add cleanup flags
CPPFLAGS += -fdata-sections -ffunction-sections
Index: u-boot-v2.git/arch/arm/cpu/Makefile
===================================================================
--- u-boot-v2.git.orig/arch/arm/cpu/Makefile 2008-05-20 18:18:43.000000000
-0500
+++ u-boot-v2.git/arch/arm/cpu/Makefile 2008-05-20 18:20:54.000000000 -0500
@@ -6,4 +6,5 @@
#
obj-$(CONFIG_ARM920T) += start-arm.o
obj-$(CONFIG_ARM926EJS) += start-arm.o
+obj-$(CONFIG_ARMCORTEXA8) += start-arm.o
obj-$(CONFIG_ARCH_IMX31) += start-arm.o
Index: u-boot-v2.git/arch/arm/cpu/start-arm.S
===================================================================
--- u-boot-v2.git.orig/arch/arm/cpu/start-arm.S 2008-05-20 18:20:54.000000000
-0500
+++ u-boot-v2.git/arch/arm/cpu/start-arm.S 2008-05-21 10:44:14.000000000
-0500
@@ -143,12 +143,66 @@
#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
bl arch_init_lowlevel
#endif
+
+#ifdef CONFIG_ARMCORTEXA8
+ /*
+ * Invalidate v7 I/D caches
+ */
+ mov r0, #0 /* set up for MCR */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
+ /* Invalidate all Dcaches */
+#ifndef CONFIG_ARMCORTEXA8_DCACHE_SKIP
+ /* If Arch specific ROM code SMI handling does not exist */
+ mrc p15, 1, r0, c0, c0, 1 /* read clidr */
+ ands r3, r0, #0x7000000 /* extract loc from clidr */
+ mov r3, r3, lsr #23 /* left align loc bit field */
+ beq finished_inval /* if loc is 0, then no need to clean */
+ mov r10, #0 /* start clean at cache level 0 */
+inval_loop1:
+ add r2, r10, r10, lsr #1 /* work out 3x current cache level */
+ mov r1, r0, lsr r2 /* extract cache type bits from clidr */
+ and r1, r1, #7 /* mask of the bits for current cache only */
+ cmp r1, #2 /* see what cache we have at this level */
+ blt skip_inval /* skip if no cache, or just i-cache */
+ mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
+ isb /* isb to sych the new cssr&csidr */
+ mrc p15, 1, r1, c0, c0, 0 /* read the new csidr */
+ and r2, r1, #7 /* extract the length of the cache lines */
+ add r2, r2, #4 /* add 4 (line length offset) */
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 /* find maximum number on the way size*/
+ clz r5, r4 /* find bit position of way size increment */
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 /* extract max number of the index size */
+inval_loop2:
+ mov r9, r4 /* create working copy of max way size */
+inval_loop3:
+ orr r11, r10, r9, lsl r5 /* factor way and cache number into r11*/
+ orr r11, r11, r7, lsl r2 /* factor index number into r11 */
+ mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
+ subs r9, r9, #1 /* decrement the way */
+ bge inval_loop3
+ subs r7, r7, #1 /* decrement the index */
+ bge inval_loop2
+skip_inval:
+ add r10, r10, #2 /* increment cache number */
+ cmp r3, r10
+ bgt inval_loop1
+finished_inval:
+ mov r10, #0 /* swith back to cache level 0 */
+ mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
+ isb
+#endif /* CONFIG_ARMCORTEXA8_DCACHE_SKIP */
+
+#else
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+#endif
/*
* disable MMU stuff and caches
-------------------------------------------------------------------------
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