These headers are used to probe and utilize CPU informartion.
- <asm/cpu-features.h>
- <asm/cpu-info.h>
- <asm/cpu.h>
- <asm/fpu.h>
- <asm/hazards.h>
Signed-off-by: Shinya Kuribayashi <[EMAIL PROTECTED]>
---
include/asm-mips/cpu-features.h | 218 +++++++++++++++++++++++++++++++
include/asm-mips/cpu-info.h | 70 ++++++++++
include/asm-mips/cpu.h | 265 ++++++++++++++++++++++++++++++++++++++
include/asm-mips/fpu.h | 42 ++++++
include/asm-mips/hazards.h | 270 +++++++++++++++++++++++++++++++++++++++
include/asm-mips/mipsregs.h | 1
6 files changed, 866 insertions(+), 0 deletions(-)
create mode 100644 include/asm-mips/cpu-features.h
create mode 100644 include/asm-mips/cpu-info.h
create mode 100644 include/asm-mips/cpu.h
create mode 100644 include/asm-mips/fpu.h
create mode 100644 include/asm-mips/hazards.h
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
new file mode 100644
index 0000000..618e7a6
--- /dev/null
+++ b/include/asm-mips/cpu-features.h
@@ -0,0 +1,218 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+
+#ifndef current_cpu_type
+#define current_cpu_type() current_cpu_data.cputype
+#endif
+
+/*
+ * SMP assumption: Options of CPU 0 are a superset of all processors.
+ * This is true for all known MIPS systems.
+ */
+#ifndef cpu_has_tlb
+#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
+#endif
+#ifndef cpu_has_4kex
+#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
+#endif
+#ifndef cpu_has_3k_cache
+#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
+#endif
+#define cpu_has_6k_cache 0
+#define cpu_has_8k_cache 0
+#ifndef cpu_has_4k_cache
+#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
+#endif
+#ifndef cpu_has_tx39_cache
+#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
+#endif
+#ifndef cpu_has_fpu
+#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
+#define raw_cpu_has_fpu (raw_current_cpu_data.options &
MIPS_CPU_FPU)
+#else
+#define raw_cpu_has_fpu cpu_has_fpu
+#endif
+#ifndef cpu_has_32fpr
+#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
+#endif
+#ifndef cpu_has_counter
+#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
+#endif
+#ifndef cpu_has_watch
+#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
+#endif
+#ifndef cpu_has_divec
+#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
+#endif
+#ifndef cpu_has_vce
+#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
+#endif
+#ifndef cpu_has_cache_cdex_p
+#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
+#endif
+#ifndef cpu_has_cache_cdex_s
+#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
+#endif
+#ifndef cpu_has_prefetch
+#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
+#endif
+#ifndef cpu_has_mcheck
+#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
+#endif
+#ifndef cpu_has_ejtag
+#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
+#endif
+#ifndef cpu_has_llsc
+#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
+#endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
+#endif
+#ifndef cpu_has_mdmx
+#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
+#endif
+#ifndef cpu_has_mips3d
+#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#endif
+#ifndef cpu_has_smartmips
+#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#endif
+#ifndef cpu_has_vtag_icache
+#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
+#endif
+#ifndef cpu_has_dc_aliases
+#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
+#endif
+#ifndef cpu_has_ic_fills_f_dc
+#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
+#endif
+#ifndef cpu_has_pindexed_dcache
+#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags &
MIPS_CACHE_PINDEX)
+#endif
+
+/*
+ * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
+ * such as the R10000 have I-Caches that snoop local stores; the embedded ones
+ * don't. For maintaining I-cache coherency this means we need to flush the
+ * D-cache all the way back to whever the I-cache does refills from, so the
+ * I-cache has a chance to see the new data at all. Then we have to flush the
+ * I-cache also.
+ * Note we may have been rescheduled and may no longer be running on the CPU
+ * that did the store so we can't optimize this into only doing the flush on
+ * the local CPU.
+ */
+#ifndef cpu_icache_snoops_remote_store
+#ifdef CONFIG_SMP
+#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags &
MIPS_IC_SNOOPS_REMOTE)
+#else
+#define cpu_icache_snoops_remote_store 1
+#endif
+#endif
+
+# ifndef cpu_has_mips32r1
+# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
+# endif
+# ifndef cpu_has_mips32r2
+# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
+# endif
+# ifndef cpu_has_mips64r1
+# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
+# endif
+# ifndef cpu_has_mips64r2
+# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
+# endif
+
+/*
+ * Shortcuts ...
+ */
+#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
+#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
+#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
+#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
+
+#ifndef cpu_has_dsp
+#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
+#endif
+
+#ifndef cpu_has_mipsmt
+#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
+#endif
+
+#ifndef cpu_has_userlocal
+#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
+#endif
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits (cpu_data[0].isa_level &
MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level &
MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs 0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 0
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex 0
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits 1
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg 1
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs 1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 1
+# endif
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
+# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
+#elif !defined(cpu_has_vint)
+# define cpu_has_vint 0
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
+# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
+#elif !defined(cpu_has_veic)
+# define cpu_has_veic 0
+#endif
+
+#ifndef cpu_has_inclusive_pcaches
+#define cpu_has_inclusive_pcaches (cpu_data[0].options &
MIPS_CPU_INCLUSIVE_CACHES)
+#endif
+
+#ifndef cpu_dcache_line_size
+#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
+#endif
+#ifndef cpu_icache_line_size
+#define cpu_icache_line_size() cpu_data[0].icache.linesz
+#endif
+#ifndef cpu_scache_line_size
+#define cpu_scache_line_size() cpu_data[0].scache.linesz
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
new file mode 100644
index 0000000..2437063
--- /dev/null
+++ b/include/asm-mips/cpu-info.h
@@ -0,0 +1,70 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_INFO_H
+#define __ASM_CPU_INFO_H
+
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+ unsigned int waysize; /* Bytes per way */
+ unsigned short sets; /* Number of lines per set */
+ unsigned char ways; /* Number of ways */
+ unsigned char linesz; /* Size of line in bytes */
+ unsigned char waybit; /* Bits to select in a cache set */
+ unsigned char flags; /* Flags describing cache properties */
+};
+
+/*
+ * Flag definitions
+ */
+#define MIPS_CACHE_NOT_PRESENT 0x00000001
+#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged
cache */
+#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
+#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
+#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
+#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
+
+struct cpuinfo_mips {
+ unsigned long udelay_val;
+ unsigned long asid_cache;
+
+ /*
+ * Capability and feature descriptor structure for MIPS CPU
+ */
+ unsigned long options;
+ unsigned long ases;
+ unsigned int processor_id;
+ unsigned int fpu_id;
+ unsigned int cputype;
+ int isa_level;
+ int tlbsize;
+ struct cache_desc icache; /* Primary I-cache */
+ struct cache_desc dcache; /* Primary D or combined I/D cache */
+ struct cache_desc scache; /* Secondary cache */
+ struct cache_desc tcache; /* Tertiary/split secondary cache */
+ int srsets; /* Shadow register sets */
+ int core; /* physical core number */
+ void *data; /* Additional data */
+} __attribute__((aligned(1UL << 5)));
+
+extern struct cpuinfo_mips cpu_data[];
+#define current_cpu_data cpu_data[0]
+#define raw_current_cpu_data cpu_data[0]
+
+extern void cpu_probe(void);
+extern void cpu_report(void);
+
+extern const char *__cpu_name[];
+#define cpu_name_string() __cpu_name[0]
+
+#endif /* __ASM_CPU_INFO_H */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
new file mode 100644
index 0000000..58715e8
--- /dev/null
+++ b/include/asm-mips/cpu.h
@@ -0,0 +1,265 @@
+/*
+ * cpu.h: Values of the PRId register used to match up
+ * various MIPS cpu types.
+ *
+ * Copyright (C) 1996 David S. Miller ([EMAIL PROTECTED])
+ * Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+/*
+ * Assigned Company values for bits 23:16 of the PRId Register
+ * (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
+ * MTI, the PRId register is defined in this (backwards compatible)
+ * way:
+ *
+ * +----------------+----------------+----------------+----------------+
+ * | Company Options| Company ID | Processor ID | Revision |
+ * +----------------+----------------+----------------+----------------+
+ * 31 24 23 16 15 8 7
+ *
+ * I don't have docs for all the previous processors, but my impression is
+ * that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
+ * spec.
+ */
+
+#define PRID_COMP_LEGACY 0x000000
+#define PRID_COMP_MIPS 0x010000
+#define PRID_COMP_BROADCOM 0x020000
+#define PRID_COMP_ALCHEMY 0x030000
+#define PRID_COMP_SIBYTE 0x040000
+#define PRID_COMP_SANDCRAFT 0x050000
+#define PRID_COMP_NXP 0x060000
+#define PRID_COMP_TOSHIBA 0x070000
+#define PRID_COMP_LSI 0x080000
+#define PRID_COMP_LEXRA 0x0b0000
+
+/*
+ * Assigned values for the product ID register. In order to detect a
+ * certain CPU type exactly eventually additional registers may need to
+ * be examined. These are valid when 23:16 == PRID_COMP_LEGACY
+ */
+#define PRID_IMP_R2000 0x0100
+#define PRID_IMP_AU1_REV1 0x0100
+#define PRID_IMP_AU1_REV2 0x0200
+#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
+#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
+#define PRID_IMP_R4000 0x0400
+#define PRID_IMP_R6000A 0x0600
+#define PRID_IMP_R10000 0x0900
+#define PRID_IMP_R4300 0x0b00
+#define PRID_IMP_VR41XX 0x0c00
+#define PRID_IMP_R12000 0x0e00
+#define PRID_IMP_R14000 0x0f00
+#define PRID_IMP_R8000 0x1000
+#define PRID_IMP_PR4450 0x1200
+#define PRID_IMP_R4600 0x2000
+#define PRID_IMP_R4700 0x2100
+#define PRID_IMP_TX39 0x2200
+#define PRID_IMP_R4640 0x2200
+#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
+#define PRID_IMP_R5000 0x2300
+#define PRID_IMP_TX49 0x2d00
+#define PRID_IMP_SONIC 0x2400
+#define PRID_IMP_MAGIC 0x2500
+#define PRID_IMP_RM7000 0x2700
+#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
+#define PRID_IMP_RM9000 0x3400
+#define PRID_IMP_R5432 0x5400
+#define PRID_IMP_R5500 0x5500
+
+#define PRID_IMP_UNKNOWN 0xff00
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_MIPS
+ */
+
+#define PRID_IMP_4KC 0x8000
+#define PRID_IMP_5KC 0x8100
+#define PRID_IMP_20KC 0x8200
+#define PRID_IMP_4KEC 0x8400
+#define PRID_IMP_4KSC 0x8600
+#define PRID_IMP_25KF 0x8800
+#define PRID_IMP_5KE 0x8900
+#define PRID_IMP_4KECR2 0x9000
+#define PRID_IMP_4KEMPR2 0x9100
+#define PRID_IMP_4KSD 0x9200
+#define PRID_IMP_24K 0x9300
+#define PRID_IMP_34K 0x9500
+#define PRID_IMP_24KE 0x9600
+#define PRID_IMP_74K 0x9700
+#define PRID_IMP_1004K 0x9900
+#define PRID_IMP_LOONGSON1 0x4200
+#define PRID_IMP_LOONGSON2 0x6300
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
+ */
+
+#define PRID_IMP_SB1 0x0100
+#define PRID_IMP_SB1A 0x1100
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
+ */
+
+#define PRID_IMP_SR71000 0x0400
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
+ */
+
+#define PRID_IMP_BCM4710 0x4000
+#define PRID_IMP_BCM3302 0x9000
+
+/*
+ * Definitions for 7:0 on legacy processors
+ */
+
+#define PRID_REV_MASK 0x00ff
+
+#define PRID_REV_TX4927 0x0022
+#define PRID_REV_TX4937 0x0030
+#define PRID_REV_R4400 0x0040
+#define PRID_REV_R3000A 0x0030
+#define PRID_REV_R3000 0x0020
+#define PRID_REV_R2000A 0x0010
+#define PRID_REV_TX3912 0x0010
+#define PRID_REV_TX3922 0x0030
+#define PRID_REV_TX3927 0x0040
+#define PRID_REV_VR4111 0x0050
+#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
+#define PRID_REV_VR4121 0x0060
+#define PRID_REV_VR4122 0x0070
+#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
+#define PRID_REV_VR4130 0x0080
+#define PRID_REV_34K_V1_0_2 0x0022
+
+/*
+ * Older processors used to encode processor version and revision in two
+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
+ * the patch number. *ARGH*
+ */
+#define PRID_REV_ENCODE_44(ver, rev) \
+ ((ver) << 4 | (rev))
+#define PRID_REV_ENCODE_332(ver, rev, patch) \
+ ((ver) << 5 | (rev) << 2 | (patch))
+
+/*
+ * FPU implementation/revision register (CP1 control register 0).
+ *
+ * +---------------------------------+----------------+----------------+
+ * | 0 | Implementation | Revision |
+ * +---------------------------------+----------------+----------------+
+ * 31 16 15 8 7 0
+ */
+
+#define FPIR_IMP_NONE 0x0000
+
+enum cpu_type_enum {
+ CPU_UNKNOWN,
+
+ /*
+ * R2000 class processors
+ */
+ CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
+ CPU_R3081, CPU_R3081E,
+
+ /*
+ * R6000 class processors
+ */
+ CPU_R6000, CPU_R6000A,
+
+ /*
+ * R4000 class processors
+ */
+ CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
+ CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
+ CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
+ CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
+ CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
+ CPU_SR71000, CPU_RM9000, CPU_TX49XX,
+
+ /*
+ * R8000 class processors
+ */
+ CPU_R8000,
+
+ /*
+ * TX3900 class processors
+ */
+ CPU_TX3912, CPU_TX3922, CPU_TX3927,
+
+ /*
+ * MIPS32 class processors
+ */
+ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
+ CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
+ CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
+
+ /*
+ * MIPS64 class processors
+ */
+ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+
+ CPU_LAST
+};
+
+/*
+ * ISA Level encodings
+ *
+ */
+#define MIPS_CPU_ISA_I 0x00000001
+#define MIPS_CPU_ISA_II 0x00000002
+#define MIPS_CPU_ISA_III 0x00000004
+#define MIPS_CPU_ISA_IV 0x00000008
+#define MIPS_CPU_ISA_V 0x00000010
+#define MIPS_CPU_ISA_M32R1 0x00000020
+#define MIPS_CPU_ISA_M32R2 0x00000040
+#define MIPS_CPU_ISA_M64R1 0x00000080
+#define MIPS_CPU_ISA_M64R2 0x00000100
+
+#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
+ MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
+#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
+ MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
+
+/*
+ * CPU Option encodings
+ */
+#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
+#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
+#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
+#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
+#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
+#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
+#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
+#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
+#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
+#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible
*/
+#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
+#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
+#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
+#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored
interrupts */
+#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external
interrupt controller mode */
+#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
+
+/*
+ * CPU ASE encodings
+ */
+#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
+#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
+#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
+#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
+#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
+#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
+
+#endif /* _ASM_CPU_H */
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
new file mode 100644
index 0000000..4d8684b
--- /dev/null
+++ b/include/asm-mips/fpu.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2002 MontaVista Software Inc.
+ * Author: Jun Sun, [EMAIL PROTECTED] or [EMAIL PROTECTED]
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_FPU_H
+#define _ASM_FPU_H
+
+#include <asm/mipsregs.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/hazards.h>
+
+#define __enable_fpu() \
+do { \
+ set_c0_status(ST0_CU1); \
+ enable_fpu_hazard(); \
+} while (0)
+
+#define __disable_fpu()
\
+do { \
+ clear_c0_status(ST0_CU1); \
+ disable_fpu_hazard(); \
+} while (0)
+
+#define enable_fpu() \
+do { \
+ if (cpu_has_fpu) \
+ __enable_fpu(); \
+} while (0)
+
+#define disable_fpu() \
+do { \
+ if (cpu_has_fpu) \
+ __disable_fpu(); \
+} while (0)
+
+#endif /* _ASM_FPU_H */
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
new file mode 100644
index 0000000..7420886
--- /dev/null
+++ b/include/asm-mips/hazards.h
@@ -0,0 +1,270 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle <[EMAIL PROTECTED]>
+ * Copyright (C) MIPS Technologies, Inc.
+ * written by Ralf Baechle <[EMAIL PROTECTED]>
+ */
+#ifndef _ASM_HAZARDS_H
+#define _ASM_HAZARDS_H
+
+#ifdef __ASSEMBLY__
+#define ASMMACRO(name, code...) .macro name; code; .endm
+#else
+
+#include <asm/cpu-features.h>
+
+#define ASMMACRO(name, code...)
\
+__asm__(".macro " #name "; " #code "; .endm"); \
+ \
+static inline void name(void) \
+{ \
+ __asm__ __volatile__ (#name); \
+}
+
+/*
+ * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
+ */
+extern void mips_ihb(void);
+
+#endif
+
+ASMMACRO(_ssnop,
+ sll $0, $0, 1
+ )
+
+ASMMACRO(_ehb,
+ sll $0, $0, 3
+ )
+
+/*
+ * TLB hazards
+ */
+#if defined(CONFIG_CPU_MIPSR2)
+
+/*
+ * MIPSR2 defines ehb for hazard avoidance
+ */
+
+ASMMACRO(mtc0_tlbw_hazard,
+ _ehb
+ )
+ASMMACRO(tlbw_use_hazard,
+ _ehb
+ )
+ASMMACRO(tlb_probe_hazard,
+ _ehb
+ )
+ASMMACRO(irq_enable_hazard,
+ _ehb
+ )
+ASMMACRO(irq_disable_hazard,
+ _ehb
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ _ehb
+ )
+/*
+ * gcc has a tradition of misscompiling the previous construct using the
+ * address of a label as argument to inline assembler. Gas otoh has the
+ * annoying difference between la and dla which are only usable for 32-bit
+ * rsp. 64-bit code, so can't be used without conditional compilation.
+ * The alterantive is switching the assembler to 64-bit code which happens
+ * to work right even for 32-bit code ...
+ */
+#define instruction_hazard() \
+do { \
+ unsigned long tmp; \
+ \
+ __asm__ __volatile__( \
+ " .set mips64r2 \n" \
+ " dla %0, 1f \n" \
+ " jr.hb %0 \n" \
+ " .set mips0 \n" \
+ "1: \n" \
+ : "=r" (tmp)); \
+} while (0)
+
+#elif defined(CONFIG_CPU_MIPSR1)
+
+/*
+ * These are slightly complicated by the fact that we guarantee R1 kernels to
+ * run fine on R2 processors.
+ */
+ASMMACRO(mtc0_tlbw_hazard,
+ _ssnop; _ssnop; _ehb
+ )
+ASMMACRO(tlbw_use_hazard,
+ _ssnop; _ssnop; _ssnop; _ehb
+ )
+ASMMACRO(tlb_probe_hazard,
+ _ssnop; _ssnop; _ssnop; _ehb
+ )
+ASMMACRO(irq_enable_hazard,
+ _ssnop; _ssnop; _ssnop; _ehb
+ )
+ASMMACRO(irq_disable_hazard,
+ _ssnop; _ssnop; _ssnop; _ehb
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ _ssnop; _ssnop; _ssnop; _ehb
+ )
+/*
+ * gcc has a tradition of misscompiling the previous construct using the
+ * address of a label as argument to inline assembler. Gas otoh has the
+ * annoying difference between la and dla which are only usable for 32-bit
+ * rsp. 64-bit code, so can't be used without conditional compilation.
+ * The alterantive is switching the assembler to 64-bit code which happens
+ * to work right even for 32-bit code ...
+ */
+#define __instruction_hazard() \
+do { \
+ unsigned long tmp; \
+ \
+ __asm__ __volatile__( \
+ " .set mips64r2 \n" \
+ " dla %0, 1f \n" \
+ " jr.hb %0 \n" \
+ " .set mips0 \n" \
+ "1: \n" \
+ : "=r" (tmp)); \
+} while (0)
+
+#define instruction_hazard() \
+do { \
+ if (cpu_has_mips_r2) \
+ __instruction_hazard(); \
+} while (0)
+
+#elif defined(CONFIG_CPU_R10000)
+
+/*
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ */
+
+ASMMACRO(mtc0_tlbw_hazard,
+ )
+ASMMACRO(tlbw_use_hazard,
+ )
+ASMMACRO(tlb_probe_hazard,
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ )
+#define instruction_hazard() do { } while (0)
+
+#elif defined(CONFIG_CPU_RM9000)
+
+/*
+ * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
+ * use of the JTLB for instructions should not occur for 4 cpu cycles and use
+ * for data translations should not occur for 3 cpu cycles.
+ */
+
+ASMMACRO(mtc0_tlbw_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(tlbw_use_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(tlb_probe_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ )
+#define instruction_hazard() do { } while (0)
+
+#elif defined(CONFIG_CPU_SB1)
+
+/*
+ * Mostly like R4000 for historic reasons
+ */
+ASMMACRO(mtc0_tlbw_hazard,
+ )
+ASMMACRO(tlbw_use_hazard,
+ )
+ASMMACRO(tlb_probe_hazard,
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ )
+#define instruction_hazard() do { } while (0)
+
+#else
+
+/*
+ * Finally the catchall case for all other processors including R4000, R4400,
+ * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
+ *
+ * The taken branch will result in a two cycle penalty for the two killed
+ * instructions on R4000 / R4400. Other processors only have a single cycle
+ * hazard so this is nice trick to have an optimal code for a range of
+ * processors.
+ */
+ASMMACRO(mtc0_tlbw_hazard,
+ nop; nop
+ )
+ASMMACRO(tlbw_use_hazard,
+ nop; nop; nop
+ )
+ASMMACRO(tlb_probe_hazard,
+ nop; nop; nop
+ )
+ASMMACRO(irq_enable_hazard,
+ _ssnop; _ssnop; _ssnop;
+ )
+ASMMACRO(irq_disable_hazard,
+ nop; nop; nop
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ _ssnop; _ssnop; _ssnop;
+ )
+#define instruction_hazard() do { } while (0)
+
+#endif
+
+/* FPU hazards */
+
+#if defined(CONFIG_CPU_SB1)
+ASMMACRO(enable_fpu_hazard,
+ .set push;
+ .set mips64;
+ .set noreorder;
+ _ssnop;
+ bnezl $0, .+4;
+ _ssnop;
+ .set pop
+)
+ASMMACRO(disable_fpu_hazard,
+)
+
+#elif defined(CONFIG_CPU_MIPSR2)
+ASMMACRO(enable_fpu_hazard,
+ _ehb
+)
+ASMMACRO(disable_fpu_hazard,
+ _ehb
+)
+#else
+ASMMACRO(enable_fpu_hazard,
+ nop; nop; nop; nop
+)
+ASMMACRO(disable_fpu_hazard,
+ _ehb
+)
+#endif
+
+#endif /* _ASM_HAZARDS_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index be7e5c6..384d2c0 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -16,6 +16,7 @@
#if 0
#include <linux/linkage.h>
#endif
+#include <asm/hazards.h>
/*
* The following macros are especially useful for __asm__
-------------------------------------------------------------------------
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