Dear Stefan,
The CPU and bus related info is hard-coded in the code. This is what I saw
from my code. Not very sure of it, though.
Yes, could be that you are using the fixed, compiled-in speed configuration.
This arises another question. Assume that both configurations (CPU and
SDRAM) are obtained from the EEPROM, how can C program/function be
adopted to use these parameters before CPU/memory is initiated? C
programs/functions need memory space to setup the stacks, which means
CPU/memory initialization should be done (via assembly) before any C
programs/functions can be used.
Thanks again for your answering.
Yi-Neng
I think it's the spd_sdram() [cpu/ppc4xx] who does the job, which could
have been an outdated method.
It was renamed and is now called 40x_spd_sdram.c. For board with DIMM modules
on 405EP this is the way to go.
The timing info is read from the SPD (Serial
Presence Detect) EEPROM on the SDRAM module. My question is, with the
upgraded CPU clock (333MHz), ordinary SDRAMs (PC100 and PC133) may not be
able to support it, which means I may have to use PC2700 (333MHz; too
fast?) or PC66(66MHz; too slow?). Am I correct? Any other comment or
solution for this?
I'm pretty sure that you still can use the "ordinary" DIMMs. The driver should
configure the needed parameters like CAS latency accordingly.
Best regards,
Stefan
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