On Wednesday 09 July 2008, Grant Erickson wrote: > While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM > controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in > the 405EX(r), SDRAM_MCSTAT has a different DCR value. > > Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF > which causes SDRAM initialization to periodically fail since it can > prematurely indicate SDRAM ready status. > > Signed-off-by: Grant Erickson <[EMAIL PROTECTED]>
Applied to "next" branch in u-boot-ppc4xx repository. Thanks. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] ===================================================================== ------------------------------------------------------------------------- Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 _______________________________________________ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
