> I have a copy of the Verilog code used in the BCSR I took a closer look at the Verilog code. Searching for the I/O port nBCSR_CS within the code shows that it is synchronized through a single register to the 33MHz clock (which comes from on-board oscillator, not the processor) to generate the signal nBCSRCSsyn.
This code is incorrect, the signal nBCSR_CS is asynchronous relative to the 33MHz clock. As such, the signal should be registered through two registers to synchronize it to the 33MHz clock domain. This synchronization error would cause multiple transient issues. These issues will not show up in simulation, as the metastability of the register outputs is not simulated (by Modelsim anyway). These issues will also show up on the hardware, regardless of the PowerPC local clock setting, as the BCSR is accessed in PowerPC LBC GPCM mode, and the CPLD is using its own 33MHz clock to generate GPCM responses. Cheers, Dave ------------------------------------------------------------------------- This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK & win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100&url=/ _______________________________________________ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
