The defines in arch/m68k/include/coldfire/flexbus.h are not compatible with the
5235 processor. The registers in struct fbcs are different sizes from those in
the 5235. Also, the defines are a little different.
This is what I have so far. Comments?
--- u-boot-denx/arch/m68k/include/asm/coldfire/flexbus.h 2011-03-02
11:02:14.000000000 -0500
+++ u-boot/include/asm-m68k/coldfire/flexbus.h 2011-02-24 13:40:07.000000000
-0500
@@ -30,6 +30,57 @@
* FlexBus Chip Selects (FBCS)
*********************************************************************/
+#ifdef CONFIG_M5235
+typedef struct fbcs {
+ u16 csar0; /* Chip-select Address */
+ u16 res1;
+ u32 csmr0; /* Chip-select Mask */
+ u16 res2;
+ u16 cscr0; /* Chip-select Control */
+
+ u16 csar1;
+ u16 res3;
+ u32 csmr1;
+ u16 res4;
+ u16 cscr1;
+
+ u16 csar2;
+ u16 res5;
+ u32 csmr2;
+ u16 res6;
+ u16 cscr2;
+
+ u16 csar3;
+ u16 res7;
+ u32 csmr3;
+ u16 res8;
+ u16 cscr3;
+
+ u16 csar4;
+ u16 res9;
+ u32 csmr4;
+ u16 res10;
+ u16 cscr4;
+
+ u16 csar5;
+ u16 res11;
+ u32 csmr5;
+ u16 res12;
+ u16 cscr5;
+
+ u16 csar6;
+ u16 res13;
+ u32 csmr6;
+ u16 res14;
+ u16 cscr6;
+
+ u16 csar7;
+ u16 res15;
+ u32 csmr7;
+ u16 res16;
+ u16 cscr7;
+} fbcs_t;
+#else
typedef struct fbcs {
u32 csar0; /* Chip-select Address */
u32 csmr0; /* Chip-select Mask */
@@ -56,6 +107,7 @@
u32 csmr7;
u32 cscr7;
} fbcs_t;
+#endif
#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
@@ -94,6 +146,22 @@
#endif
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
+#ifdef CONFIG_M5235
+#define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14)
+#define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10)
+#define FBCS_CSCR_AA_ON (1 << 8)
+#define FBCS_CSCR_AA_OFF (0 << 8)
+#define FBCS_CSCR_PS_32 (0 << 6)
+#define FBCS_CSCR_PS_16 (2 << 6)
+#define FBCS_CSCR_PS_8 (1 << 6)
+#define FBCS_CSCR_BEM_ON (1 << 5)
+#define FBCS_CSCR_BEM_OFF (0 << 5)
+#define FBCS_CSCR_BSTR_ON (1 << 4)
+#define FBCS_CSCR_BSTR_OFF (0 << 4)
+#define FBCS_CSCR_BSTW_ON (1 << 3)
+#define FBCS_CSCR_BSTW_OFF (0 << 3)
+#define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0)
+#else
#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26)
#define FBCS_CSCR_SWS_MASK (0x03FFFFFF)
#define FBCS_CSCR_SWSEN (0x00800000)
@@ -116,5 +184,6 @@
#define FBCS_CSCR_PS_16 (0x00000080)
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_32 (0x00000000)
+#endif
#endif /* __FLEXBUS_H */
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