From: Tirumala R Marri <[EMAIL PROTECTED]>
During recent PCI-E tests it has been found that current
driverl level and de-emphasis values are not set correctly.
After sweeping throgh all de-ephasis values, it was found that
0x130 is a right value. Where 0x13 is driver level and 0 is
de-emphasis.
Signed-off-by: Tirumala R Marri <[EMAIL PROTECTED]>
---
cpu/ppc4xx/4xx_pcie.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 9803fcc..0aadc06 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -638,7 +638,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
switch (port) {
case 0:
SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
- SDR_WRITE(PESDR0_L0DRV, 0x00000136);
+ SDR_WRITE(PESDR0_L0DRV, 0x00000130);
SDR_WRITE(PESDR0_L0CLK, 0x00000006);
SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
@@ -649,10 +649,10 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L0DRV, 0x00000136);
- SDR_WRITE(PESDR1_L1DRV, 0x00000136);
- SDR_WRITE(PESDR1_L2DRV, 0x00000136);
- SDR_WRITE(PESDR1_L3DRV, 0x00000136);
+ SDR_WRITE(PESDR1_L0DRV, 0x00000130);
+ SDR_WRITE(PESDR1_L1DRV, 0x00000130);
+ SDR_WRITE(PESDR1_L2DRV, 0x00000130);
+ SDR_WRITE(PESDR1_L3DRV, 0x00000130);
SDR_WRITE(PESDR1_L0CLK, 0x00000006);
SDR_WRITE(PESDR1_L1CLK, 0x00000006);
SDR_WRITE(PESDR1_L2CLK, 0x00000006);
--
1.5.3
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