From: TsiChung Liew <[EMAIL PROTECTED]>
Consolidate RNG, MDHA and SKHA structures and
definitions in immap_5xxx.h and m5xxx.h to more
unify modules header files. SSI cleanup. Remove
USB Host structure from immap_5329.h
Signed-off-by: TsiChung Liew <[EMAIL PROTECTED]>
---
include/asm-m68k/coldfire/mdha.h | 102 ++++++++++++++++++++++++++++++++
include/asm-m68k/coldfire/rng.h | 52 ++++++++++++++++
include/asm-m68k/coldfire/skha.h | 121 ++++++++++++++++++++++++++++++++++++++
include/asm-m68k/coldfire/ssi.h | 66 +++++++++-----------
include/asm-m68k/immap_5235.h | 3 +
include/asm-m68k/immap_5271.h | 3 +
include/asm-m68k/immap_5275.h | 3 +
include/asm-m68k/immap_5329.h | 116 +-----------------------------------
include/asm-m68k/immap_5445x.h | 8 ---
include/asm-m68k/m5445x.h | 18 ------
10 files changed, 316 insertions(+), 176 deletions(-)
create mode 100644 include/asm-m68k/coldfire/mdha.h
create mode 100644 include/asm-m68k/coldfire/rng.h
create mode 100644 include/asm-m68k/coldfire/skha.h
diff --git a/include/asm-m68k/coldfire/mdha.h b/include/asm-m68k/coldfire/mdha.h
new file mode 100644
index 0000000..b698136
--- /dev/null
+++ b/include/asm-m68k/coldfire/mdha.h
@@ -0,0 +1,102 @@
+/*
+ * Message Digest Hardware Accelerator Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MDHA_H__
+#define __MDHA_H__
+
+/* Message Digest Hardware Accelerator */
+typedef struct mdha_ctrl {
+ u32 mr; /* 0x00 MDHA Mode */
+ u32 cr; /* 0x04 Control */
+ u32 cmd; /* 0x08 Command */
+ u32 sr; /* 0x0C Status */
+ u32 isr; /* 0x10 Interrupt Status */
+ u32 imr; /* 0x14 Interrupt Mask */
+ u32 dsz; /* 0x1C Data Size */
+ u32 inp; /* 0x20 Input FIFO */
+ u32 res1[3]; /* 0x24 - 0x2F */
+ u32 mda0; /* 0x30 Message Digest AO */
+ u32 mdb0; /* 0x34 Message Digest BO */
+ u32 mdc0; /* 0x38 Message Digest CO */
+ u32 mdd0; /* 0x3C Message Digest DO */
+ u32 mde0; /* 0x40 Message Digest EO */
+ u32 mdsz; /* 0x44 Message Data Size */
+ u32 res[10]; /* 0x48 - 0x6F */
+ u32 mda1; /* 0x70 Message Digest A1 */
+ u32 mdb1; /* 0x74 Message Digest B1 */
+ u32 mdc1; /* 0x78 Message Digest C1 */
+ u32 mdd1; /* 0x7C Message Digest D1 */
+ u32 mde1; /* 0x80 Message Digest E1 */
+} mdha_t;
+
+#define MDHA_MR_SSL (0x00000400)
+#define MDHA_MR_MACFUL (0x00000200)
+#define MDHA_MR_SWAP (0x00000100)
+#define MDHA_MR_OPAD (0x00000080)
+#define MDHA_MR_IPAD (0x00000040)
+#define MDHA_MR_INIT (0x00000020)
+#define MDHA_MR_MAC(x) (((x) & 0x03) << 3)
+#define MDHA_MR_MAC_MASK (0xFFFFFFE7)
+#define MDHA_MR_MAC_EHMAC (0x00000010)
+#define MDHA_MR_MAC_HMAC (0x00000008)
+#define MDHA_MR_MAC_NONE (0x00000000)
+#define MDHA_MR_PDATA (0x00000004)
+#define MDHA_MR_ALG (0x00000001)
+
+#define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */
+#define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */
+#define MDHA_CR_END (0x00000004) /* 532x */
+#define MDHA_CR_DMA (0x00000002) /* 532x */
+#define MDHA_CR_IE (0x00000001)
+
+#define MDHA_CMD_GO (0x00000008)
+#define MDHA_CMD_CI (0x00000004)
+#define MDHA_CMD_RI (0x00000001)
+#define MDHA_CMD_SWR (0x00000001)
+
+#define MDHA_SR_IFL(x) (((x) & 0xFF) << 16)
+#define MDHA_SR_IFL_MASK (0xFF00FFFF)
+#define MDHA_SR_APD(x) (((x) & 0x7) << 13)
+#define MDHA_SR_APD_MASK (0xFFFF1FFF)
+#define MDHA_SR_FS(x) (((x) & 0x7) << 8)
+#define MDHA_SR_FS_MASK (0xFFFFF8FF)
+#define MDHA_SR_GNW (0x00000080)
+#define MDHA_SR_HSH (0x00000040)
+#define MDHA_SR_BUSY (0x00000010)
+#define MDHA_SR_RD (0x00000008)
+#define MDHA_SR_ERR (0x00000004)
+#define MDHA_SR_DONE (0x00000002)
+#define MDHA_SR_INT (0x00000001)
+
+#define MDHA_ISR_DRL (0x00000400) /* 532x */
+#define MDHA_ISR_GTDS (0x00000200)
+#define MDHA_ISR_ERE (0x00000100)
+#define MDHA_ISR_RMDP (0x00000080)
+#define MDHA_ISR_DSE (0x00000020)
+#define MDHA_ISR_IME (0x00000010)
+#define MDHA_ISR_NEIF (0x00000004)
+#define MDHA_ISR_IFO (0x00000001)
+
+#endif /* __MDHA_H__ */
diff --git a/include/asm-m68k/coldfire/rng.h b/include/asm-m68k/coldfire/rng.h
new file mode 100644
index 0000000..1eefc56
--- /dev/null
+++ b/include/asm-m68k/coldfire/rng.h
@@ -0,0 +1,52 @@
+/*
+ * RNG Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __RNG_H__
+#define __RNG_H__
+
+/* Random Number Generator */
+typedef struct rng_ctrl {
+ u32 cr; /* 0x00 Control */
+ u32 sr; /* 0x04 Status */
+ u32 er; /* 0x08 Entropy */
+ u32 out; /* 0x0C Output FIFO */
+} rng_t;
+
+#define RNG_CR_SLM (0x00000010) /* Sleep mode - 5445x */
+#define RNG_CR_CI (0x00000008) /* Clear interrupt */
+#define RNG_CR_IM (0x00000004) /* Interrupt mask */
+#define RNG_CR_HA (0x00000002) /* High assurance */
+#define RNG_CR_GO (0x00000001) /* Go bit */
+
+#define RNG_SR_OFS(x) (((x) & 0x000000FF) << 16)
+#define RNG_SR_OFS_MASK (0xFF00FFFF)
+#define RNG_SR_OFL(x) (((x) & 0x000000FF) << 8)
+#define RNG_SR_OFL_MASK (0xFFFF00FF)
+#define RNG_SR_EI (0x00000008)
+#define RNG_SR_FUF (0x00000004)
+#define RNG_SR_LRS (0x00000002)
+#define RNG_SR_SV (0x00000001)
+
+#endif /* __RNG_H__ */
diff --git a/include/asm-m68k/coldfire/skha.h b/include/asm-m68k/coldfire/skha.h
new file mode 100644
index 0000000..bd6b5af
--- /dev/null
+++ b/include/asm-m68k/coldfire/skha.h
@@ -0,0 +1,121 @@
+/*
+ * Symmetric Key Hardware Accelerator Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew ([EMAIL PROTECTED])
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SKHA_H__
+#define __SKHA_H__
+
+typedef struct skha_ctrl {
+ u32 mr; /* 0x00 Mode */
+ u32 cr; /* 0x04 Control */
+ u32 cmr; /* 0x08 Command */
+ u32 sr; /* 0x0C Status */
+ u32 esr; /* 0x10 Error Status */
+ u32 emr; /* 0x14 Error Status Mask Register) */
+ u32 ksr; /* 0x18 Key Size */
+ u32 dsr; /* 0x1C Data Size */
+ u32 in; /* 0x20 Input FIFO */
+ u32 out; /* 0x24 Output FIFO */
+ u32 res1[2]; /* 0x28 - 0x2F */
+ u32 kdr1; /* 0x30 Key Data 1 */
+ u32 kdr2; /* 0x34 Key Data 2 */
+ u32 kdr3; /* 0x38 Key Data 3 */
+ u32 kdr4; /* 0x3C Key Data 4 */
+ u32 kdr5; /* 0x40 Key Data 5 */
+ u32 kdr6; /* 0x44 Key Data 6 */
+ u32 res2[10]; /* 0x48 - 0x6F */
+ u32 c1; /* 0x70 Context 1 */
+ u32 c2; /* 0x74 Context 2 */
+ u32 c3; /* 0x78 Context 3 */
+ u32 c4; /* 0x7C Context 4 */
+ u32 c5; /* 0x80 Context 5 */
+ u32 c6; /* 0x84 Context 6 */
+ u32 c7; /* 0x88 Context 7 */
+ u32 c8; /* 0x8C Context 8 */
+ u32 c9; /* 0x90 Context 9 */
+ u32 c10; /* 0x94 Context 10 */
+ u32 c11; /* 0x98 Context 11 */
+ u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */
+} skha_t;
+
+#ifdef CONFIG_MCF532x
+#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9)
+#define SKHA_MODE_CTRM_MASK (0xFFFFE1FF)
+#define SKHA_MODE_DKP (0x00000100)
+#else
+#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8)
+#define SKHA_MODE_CTRM_MASK (0xFFFFF0FF)
+#define SKHA_MODE_DKP (0x00000080)
+#endif
+#define SKHA_MODE_CM(x) (((x) & 0x03) << 3)
+#define SKHA_MODE_CM_MASK (0xFFFFFFE7)
+#define SKHA_MODE_DIR (0x00000004)
+#define SKHA_MODE_ALG(x) ((x) & 0x03)
+#define SKHA_MODE_ALG_MASK (0xFFFFFFFC)
+
+#define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24)
+#define SHKA_CR_ODMAL_MASK (0xC0FFFFFF)
+#define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16)
+#define SHKA_CR_IDMAL_MASK (0xFFC0FFFF)
+#define SHKA_CR_END (0x00000008)
+#define SHKA_CR_ODMA (0x00000004)
+#define SHKA_CR_IDMA (0x00000002)
+#define SKHA_CR_IE (0x00000001)
+
+#define SKHA_CMR_GO (0x00000008)
+#define SKHA_CMR_CI (0x00000004)
+#define SKHA_CMR_RI (0x00000002)
+#define SKHA_CMR_SWR (0x00000001)
+
+#define SKHA_SR_OFL(x) (((x) & 0xFF) << 24)
+#define SKHA_SR_OFL_MASK (0x00FFFFFF)
+#define SKHA_SR_IFL(x) (((x) & 0xFF) << 16)
+#define SKHA_SR_IFL_MASK (0xFF00FFFF)
+#define SKHA_SR_AESES(x) (((x) & 0x1F) << 11)
+#define SKHA_SR_AESES_MASK (0xFFFF07FF)
+#define SKHA_SR_DESES(x) (((x) & 0x7) << 8)
+#define SKHA_SR_DESES_MASK (0xFFFFF8FF)
+#define SKHA_SR_BUSY (0x00000010)
+#define SKHA_SR_RD (0x00000008)
+#define SKHA_SR_ERR (0x00000004)
+#define SKHA_SR_DONE (0x00000002)
+#define SKHA_SR_INT (0x00000001)
+
+#define SHKA_ESE_DRL (0x00000800)
+#define SKHA_ESR_KRE (0x00000400)
+#define SKHA_ESR_KPE (0x00000200)
+#define SKHA_ESR_ERE (0x00000100)
+#define SKHA_ESR_RMDP (0x00000080)
+#define SKHA_ESR_KSE (0x00000040)
+#define SKHA_ESR_DSE (0x00000020)
+#define SKHA_ESR_IME (0x00000010)
+#define SKHA_ESR_NEOF (0x00000008)
+#define SKHA_ESR_NEIF (0x00000004)
+#define SKHA_ESR_OFU (0x00000002)
+#define SKHA_ESR_IFO (0x00000001)
+
+#define SKHA_KSR_SZ(x) ((x) & 0x3F)
+#define SKHA_KSR_SZ_MASK (0xFFFFFFC0)
+
+#endif /* __SKHA_H__ */
diff --git a/include/asm-m68k/coldfire/ssi.h b/include/asm-m68k/coldfire/ssi.h
index 105c475..b3dfbfa 100644
--- a/include/asm-m68k/coldfire/ssi.h
+++ b/include/asm-m68k/coldfire/ssi.h
@@ -26,10 +26,6 @@
#ifndef __SSI_H__
#define __SSI_H__
-/*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-
typedef struct ssi {
u32 tx0;
u32 tx1;
@@ -52,14 +48,10 @@ typedef struct ssi {
u32 rmask;
} ssi_t;
-/*********************************************************************
-* Synchronous Serial Interface (SSI)
-*********************************************************************/
-
-/* Bit definitions and macros for SSI_CR */
#define SSI_CR_CIS (0x00000200)
#define SSI_CR_TCH (0x00000100)
#define SSI_CR_MCE (0x00000080)
+#define SSI_CR_I2S_MASK (0xFFFFFF9F)
#define SSI_CR_I2S_SLAVE (0x00000040)
#define SSI_CR_I2S_MASTER (0x00000020)
#define SSI_CR_I2S_NORMAL (0x00000000)
@@ -69,7 +61,6 @@ typedef struct ssi {
#define SSI_CR_TE (0x00000002)
#define SSI_CR_SSI_EN (0x00000001)
-/* Bit definitions and macros for SSI_ISR */
#define SSI_ISR_CMDAU (0x00040000)
#define SSI_ISR_CMDDU (0x00020000)
#define SSI_ISR_RXT (0x00010000)
@@ -90,7 +81,6 @@ typedef struct ssi {
#define SSI_ISR_TFE1 (0x00000002)
#define SSI_ISR_TFE0 (0x00000001)
-/* Bit definitions and macros for SSI_IER */
#define SSI_IER_RDMAE (0x00400000)
#define SSI_IER_RIE (0x00200000)
#define SSI_IER_TDMAE (0x00100000)
@@ -115,7 +105,6 @@ typedef struct ssi {
#define SSI_IER_TFE1 (0x00000002)
#define SSI_IER_TFE0 (0x00000001)
-/* Bit definitions and macros for SSI_TCR */
#define SSI_TCR_TXBIT0 (0x00000200)
#define SSI_TCR_TFEN1 (0x00000100)
#define SSI_TCR_TFEN0 (0x00000080)
@@ -127,7 +116,6 @@ typedef struct ssi {
#define SSI_TCR_TFSL (0x00000002)
#define SSI_TCR_TEFS (0x00000001)
-/* Bit definitions and macros for SSI_RCR */
#define SSI_RCR_RXEXT (0x00000400)
#define SSI_RCR_RXBIT0 (0x00000200)
#define SSI_RCR_RFEN1 (0x00000100)
@@ -138,38 +126,44 @@ typedef struct ssi {
#define SSI_RCR_RFSL (0x00000002)
#define SSI_RCR_REFS (0x00000001)
-/* Bit definitions and macros for SSI_CCR */
#define SSI_CCR_DIV2 (0x00040000)
#define SSI_CCR_PSR (0x00020000)
-#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
-#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
-#define SSI_CCR_PM(x) ((x)&0x000000FF)
-
-/* Bit definitions and macros for SSI_FCSR */
-#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
-#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
-#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
-#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
-#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
-#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
-#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
-#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
-
-/* Bit definitions and macros for SSI_ACR */
-#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
+#define SSI_CCR_WL(x) (((x) & 0x0F) << 13)
+#define SSI_CCR_WL_MASK (0xFFFE1FFF)
+#define SSI_CCR_DC(x) (((x)& 0x1F) << 8)
+#define SSI_CCR_DC_MASK (0xFFFFE0FF)
+#define SSI_CCR_PM(x) ((x) & 0xFF)
+#define SSI_CCR_PM_MASK (0xFFFFFF00)
+
+#define SSI_FCSR_RFCNT1(x) (((x) & 0x0F) << 28)
+#define SSI_FCSR_RFCNT1_MASK (0x0FFFFFFF)
+#define SSI_FCSR_TFCNT1(x) (((x) & 0x0F) << 24)
+#define SSI_FCSR_TFCNT1_MASK (0xF0FFFFFF)
+#define SSI_FCSR_RFWM1(x) (((x) & 0x0F) << 20)
+#define SSI_FCSR_RFWM1_MASK (0xFF0FFFFF)
+#define SSI_FCSR_TFWM1(x) (((x) & 0x0F) << 16)
+#define SSI_FCSR_TFWM1_MASK (0xFFF0FFFF)
+#define SSI_FCSR_RFCNT0(x) (((x) & 0x0F) << 12)
+#define SSI_FCSR_RFCNT0_MASK (0xFFFF0FFF)
+#define SSI_FCSR_TFCNT0(x) (((x) & 0x0F) << 8)
+#define SSI_FCSR_TFCNT0_MASK (0xFFFFF0FF)
+#define SSI_FCSR_RFWM0(x) (((x) & 0x0F) << 4)
+#define SSI_FCSR_RFWM0_MASK (0xFFFFFF0F)
+#define SSI_FCSR_TFWM0(x) ((x) & 0x0F)
+#define SSI_FCSR_TFWM0_MASK (0xFFFFFFF0)
+
+#define SSI_ACR_FRDIV(x) (((x) & 0x3F) << 5)
+#define SSI_ACR_FRDIV_MASK (0xFFFFF81F)
#define SSI_ACR_WR (0x00000010)
#define SSI_ACR_RD (0x00000008)
#define SSI_ACR_TIF (0x00000004)
#define SSI_ACR_FV (0x00000002)
#define SSI_ACR_AC97EN (0x00000001)
-/* Bit definitions and macros for SSI_ACADD */
-#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
+#define SSI_ACADD_SSI_ACADD(x) ((x) & 0x0007FFFF)
-/* Bit definitions and macros for SSI_ACDAT */
-#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
+#define SSI_ACDAT_SSI_ACDAT(x) ((x) & 0x0007FFFF)
-/* Bit definitions and macros for SSI_ATAG */
-#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
+#define SSI_ATAG_DDI_ATAG(x) ((x) & 0x0000FFFF)
#endif /* __SSI_H__ */
diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h
index 8fdf32a..ce577fe 100644
--- a/include/asm-m68k/immap_5235.h
+++ b/include/asm-m68k/immap_5235.h
@@ -65,7 +65,10 @@
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/mdha.h>
#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
/* System Control Module register */
typedef struct scm_ctrl {
diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h
index 8483501..c4d9a55 100644
--- a/include/asm-m68k/immap_5271.h
+++ b/include/asm-m68k/immap_5271.h
@@ -64,7 +64,10 @@
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/mdha.h>
#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
/* Interrupt module registers */
typedef struct int0_ctrl {
diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h
index 90143c8..d0da60e 100644
--- a/include/asm-m68k/immap_5275.h
+++ b/include/asm-m68k/immap_5275.h
@@ -67,8 +67,11 @@
#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/mdha.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
/* System configuration registers
*/
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index c32caf5..3d64168 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -75,8 +75,10 @@
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/lcd.h>
+#include <asm/coldfire/mdha.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
+#include <asm/coldfire/skha.h>
/* System control module registers */
typedef struct scm1_ctrl {
@@ -87,72 +89,6 @@ typedef struct scm1_ctrl {
u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
} scm1_t;
-/* Message Digest Hardware Accelerator */
-typedef struct mdha_ctrl {
- u32 mdmr; /* 0x00 MDHA Mode Register */
- u32 mdcr; /* 0x04 Control register */
- u32 mdcmr; /* 0x08 Command Register */
- u32 mdsr; /* 0x0C Status Register */
- u32 mdisr; /* 0x10 Interrupt Status Register */
- u32 mdimr; /* 0x14 Interrupt Mask Register */
- u32 mddsr; /* 0x1C Data Size Register */
- u32 mdin; /* 0x20 Input FIFO */
- u32 res1[3]; /* 0x24 - 0x2F */
- u32 mdao; /* 0x30 Message Digest AO Register */
- u32 mdbo; /* 0x34 Message Digest BO Register */
- u32 mdco; /* 0x38 Message Digest CO Register */
- u32 mddo; /* 0x3C Message Digest DO Register */
- u32 mdeo; /* 0x40 Message Digest EO Register */
- u32 mdmds; /* 0x44 Message Data Size Register */
- u32 res[10]; /* 0x48 - 0x6F */
- u32 mda1; /* 0x70 Message Digest A1 Register */
- u32 mdb1; /* 0x74 Message Digest B1 Register */
- u32 mdc1; /* 0x78 Message Digest C1 Register */
- u32 mdd1; /* 0x7C Message Digest D1 Register */
- u32 mde1; /* 0x80 Message Digest E1 Register */
-} mdha_t;
-
-/* Symmetric Key Hardware Accelerator */
-typedef struct skha_ctrl {
- u32 mr; /* 0x00 Mode Register */
- u32 cr; /* 0x04 Control Register */
- u32 cmr; /* 0x08 Command Register */
- u32 sr; /* 0x0C Status Register */
- u32 esr; /* 0x10 Error Status Register */
- u32 emr; /* 0x14 Error Status Mask Register) */
- u32 ksr; /* 0x18 Key Size Register */
- u32 dsr; /* 0x1C Data Size Register */
- u32 in; /* 0x20 Input FIFO */
- u32 out; /* 0x24 Output FIFO */
- u32 res1[2]; /* 0x28 - 0x2F */
- u32 kdr1; /* 0x30 Key Data Register 1 */
- u32 kdr2; /* 0x34 Key Data Register 2 */
- u32 kdr3; /* 0x38 Key Data Register 3 */
- u32 kdr4; /* 0x3C Key Data Register 4 */
- u32 kdr5; /* 0x40 Key Data Register 5 */
- u32 kdr6; /* 0x44 Key Data Register 6 */
- u32 res2[10]; /* 0x48 - 0x6F */
- u32 c1; /* 0x70 Context 1 */
- u32 c2; /* 0x74 Context 2 */
- u32 c3; /* 0x78 Context 3 */
- u32 c4; /* 0x7C Context 4 */
- u32 c5; /* 0x80 Context 5 */
- u32 c6; /* 0x84 Context 6 */
- u32 c7; /* 0x88 Context 7 */
- u32 c8; /* 0x8C Context 8 */
- u32 c9; /* 0x90 Context 9 */
- u32 c10; /* 0x94 Context 10 */
- u32 c11; /* 0x98 Context 11 */
-} skha_t;
-
-/* Random Number Generator */
-typedef struct rng_ctrl {
- u32 rngcr; /* 0x00 RNG Control Register */
- u32 rngsr; /* 0x04 RNG Status Register */
- u32 rnger; /* 0x08 RNG Entropy Register */
- u32 rngout; /* 0x0C RNG Output FIFO */
-} rng_t;
-
/* System control module registers 2 */
typedef struct scm2_ctrl {
u32 mpr1; /* 0x00 Master Privilege Register */
@@ -169,7 +105,6 @@ typedef struct scm2_ctrl {
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
-
/* System Control Module register 3 */
typedef struct scm3_ctrl {
u8 res1[19]; /* 0x00 - 0x12 */
@@ -516,53 +451,6 @@ typedef struct usb_otg {
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbotg_t;
-/* USB Host module registers */
-typedef struct usb_host {
- u32 id; /* 0x000 Identification Register */
- u32 hwgeneral; /* 0x004 General HW Parameters */
- u32 hwhost; /* 0x008 Host HW Parameters */
- u32 res1; /* 0x0C */
- u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
- u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
- u32 res2[58]; /* 0x18 - 0xFF */
-
- /* Host Controller Capability Register */
- u8 caplength; /* 0x100 Capability Register Length */
- u8 res3; /* 0x101 */
- u16 hciver; /* 0x102 Host Interface Version Number */
- u32 hcsparams; /* 0x104 Host Structural Parameters */
- u32 hccparams; /* 0x108 Host Capability Parameters */
- u32 res4[13]; /* 0x10C - 0x13F */
-
- /* Host Controller Operational Register */
- u32 cmd; /* 0x140 USB Command */
- u32 sts; /* 0x144 USB Status */
- u32 intr; /* 0x148 USB Interrupt Enable */
- u32 frindex; /* 0x14C USB Frame Index */
- u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */
- u32 prdlst; /* 0x154 Periodic Frame List Base Address */
- u32 aynclst; /* 0x158 Current Asynchronous List Address */
- u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control
(non-ehci) */
- u32 burstsize; /* 0x160 Master Interface Data Burst Size
(non-ehci) */
- u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control
(non-ehci) */
- u32 res6[6]; /* 0x168 - 0x17F */
- u32 cfgflag; /* 0x180 Configure Flag Register */
- u32 portsc1; /* 0x184 Port Status/Control */
- u32 res7[8]; /* 0x188 - 0x1A7 */
-
- /* non-ehci registers */
- u32 mode; /* 0x1A8 USB mode register */
- u32 eptsetstat; /* 0x1AC Endpoint Setup status */
- u32 eptprime; /* 0x1B0 Endpoint initialization */
- u32 eptflush; /* 0x1B4 Endpoint de-initialize */
- u32 eptstat; /* 0x1B8 Endpoint status */
- u32 eptcomplete; /* 0x1BC Endpoint Complete */
- u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
- u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
- u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
- u32 eptctrl3; /* 0x1CC Endpoint control 3 */
-} usbhost_t;
-
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode register */
diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h
index 38b767f..822a2b3 100644
--- a/include/asm-m68k/immap_5445x.h
+++ b/include/asm-m68k/immap_5445x.h
@@ -329,14 +329,6 @@ typedef struct gpio {
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
-/* Random Number Generator (RNG) */
-typedef struct rng {
- u32 rngcr;
- u32 rngsr;
- u32 rnger;
- u32 rngout;
-} rng_t;
-
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
index 69d4aac..e12ac0e 100644
--- a/include/asm-m68k/m5445x.h
+++ b/include/asm-m68k/m5445x.h
@@ -950,24 +950,6 @@
#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
/*********************************************************************
-* Random Number Generator (RNG)
-*********************************************************************/
-
-/* Bit definitions and macros for RNGCR */
-#define RNG_RNGCR_GO (0x00000001)
-#define RNG_RNGCR_HA (0x00000002)
-#define RNG_RNGCR_IM (0x00000004)
-#define RNG_RNGCR_CI (0x00000008)
-
-/* Bit definitions and macros for RNGSR */
-#define RNG_RNGSR_SV (0x00000001)
-#define RNG_RNGSR_LRS (0x00000002)
-#define RNG_RNGSR_FUF (0x00000004)
-#define RNG_RNGSR_EI (0x00000008)
-#define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
-#define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
-
-/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
--
1.5.6.4
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