Hi Wolfgang,
On Thursday 23 October 2008, Wolfgang Denk wrote:
> > > Should we not backout the autocalib patches that cause the problem
> > > until a stable working solution is found?
> >
> > Not sure. My hope is that AMCC find a solution quickly. They should
> > receive the failing board this week.
> >
> > And they already did send a "fix" (more a workaround) for this problem:
> >
> > [PATCH v2] ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz
> >
> > which you rejected. So I suggest to wait for a few days.
>
> Well, that was one full month ago, and nothing happened since.1s
That's not correct. One patch got checked in which definitely made the
situation better:
f8a00dea841d5d75de1f8e8107e90ee1beeddf5f
ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.
Signed-off-by: Adam Graham <[EMAIL PROTECTED]>
Signed-off-by: Victor Gallardo <[EMAIL PROTECTED]>
Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
Unfortunately it didn't fix all problems. AMCC already provided another patch
for testing purposes. Not to the list but to me (and you) directly. Please
find it attached again. Would be great if Markus could test it on the failing
Kilauea.
> I see people running into problems with the current code, so I vote
> to back out the culprit until a real fix has been found.
Hmmm, "people" have been running into this problem before too. That we me.
Again, let's please wait at least for Adam and/or Victor to comment on this
issue. It should only be a few hours until they read their mails.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED]
=====================================================================
--- Begin Message ---
Signed-off-by: Adam Graham <[EMAIL PROTECTED]>
---
cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 47ab39b..c63315b 100644
--- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -174,6 +174,22 @@ static inline void ecc_clear_status_reg(void)
#endif
}
+#define SDRAM_FCSR_RxMOS 0x00008000 /* rank missed oversample */
+#define SDRAM_FCSR_CMOS_MASK 0x00000030 /* hit/missed oversample */
+#define SDRAM_FCSR_CMOS_MISSED 0x00000010 /* hit/missed oversample */
+
+static inline int check_fcsr_oversample_miss(int membank)
+{
+ u32 fcsr;
+
+ mfsdram(SDRAM_FCSR, fcsr);
+ if (fcsr & (SDRAM_FCSR_RxMOS >> membank))
+ if (fcsr & SDRAM_FCSR_CMOS_MISSED)
+ return 0; /* don't count this pass */
+
+ return 1;
+}
+
/*
* Reset and relock memory DLL after SDRAM_CLKTR change
*/
@@ -783,10 +799,20 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
in_window = 1;
curr_win_min = curr_win_max = rffd;
mfsdram(SDRAM_RDCC, rdcc); /* record this value */
+
+ if (!(check_fcsr_oversample_miss(bxcr_num)))
+ pass = 0;
} else if (!pass && in_window) { /* end passing window */
in_window = 0;
+ break; /* exit end of window */
} else if (pass && in_window) { /* within the passing window */
curr_win_max = rffd;
+
+ if (!(check_fcsr_oversample_miss(bxcr_num))) {
+ pass = 0;
+ in_window = 0;
+ break; /* exit end of window */
+ }
}
if (in_window) {
@@ -849,6 +875,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
curr_win_min = curr_win_max = rqfd;
} else if (!pass && in_window) {
in_window = 0;
+ break; /* exit end of window */
} else if (pass && in_window) {
curr_win_max = rqfd;
}
--
1.5.5
--- End Message ---
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