Wolfgang Denk wrote:
> Dear [EMAIL PROTECTED],
>
> In message <[EMAIL PROTECTED]> you wrote:
>
>>--===============1314021165==
>>
>>From: Dirk Behme <[EMAIL PROTECTED]>
>>
>>Add ARM Cortex A8 common directory
>>
>>Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
>
> ...
>
>
>>+static void cp_delay(void)
>>+{
>>+ volatile int i;
>>+
>>+ /* Many OMAP regs need at least 2 nops */
>>+ for (i = 0; i < 100; i++) ;
>
>
> There is not much reason for the compiler not to optimize this code
> away.
>
>
>>+void icache_disable(void)
>>+{
>>+ ulong reg;
>>+
>>+ reg = read_p15_c1();
>>+ cp_delay();
>>+ write_p15_c1(reg & ~C1_IC);
>>+}
>>+
>>+void dcache_disable (void)
>>+{
>>+ ulong reg;
>>+
>>+ reg = read_p15_c1 ();
>>+ cp_delay ();
>>+ write_p15_c1 (reg & ~C1_DC);
>>+}
>
>
> Would it make sense to flush caches before disbling?
Basically yes. But regarding the logic used in existing code, e.g.
cpu/arm1176/cpu.c (cleanup_before_linux())
I'm not sure about this. The logic seems to be to provide single
functions for each cache operation and then call the functions in the
correct order.
>>+ /* someone ought to write a more effiction fiq_save_user_regs */
>
>
> effiction ?
>
>
> Best regards,
>
> Wolfgang Denk
>
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