Hi,
I have tried modifying the Start.s of uboot as mentioned below.
When I try to link I get an error "`.bootpg' can't be allocated in
segment 1".
Can someone guide me on this. I am also attaching the start.o and the
linker script that I am using along with this mail.
When I see the dump of start.o I find that it occupies space around
0x1c0, let say max 0x200.
But why then I get this error as this is less than the 4K page mapped.
Should I change anything let me know.
Start.S
=========
#----------------------------------------------------------
# Header File for Various constants Related to 85xx
#----------------------------------------------------------
#include "init85xx.h"
.section .bootpg,"ax"
.globl _start_e500
_start_e500:
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
# setup ccsrbar
bl setup_ccsrbar
#endif
/* create a temp mapping in AS=1 to the CCSRBAR */
lis %r6, [EMAIL PROTECTED]
ori %r6, %r6, [EMAIL PROTECTED]
lis %r7, [EMAIL PROTECTED]
ori %r7, %r7, [EMAIL PROTECTED]
lis %r8, [EMAIL PROTECTED]
ori %r8, %r8, [EMAIL PROTECTED]
lis %r9, [EMAIL PROTECTED]
ori %r9, %r9, [EMAIL PROTECTED]
mtspr MAS0,%r6
mtspr MAS1,%r7
mtspr MAS2,%r8
mtspr MAS3,%r9
isync
msync
tlbwe
tlbre
/* clear registers/arrays not reset by hardware */
/* L1 */
li %r0,2
mtspr L1CSR0,%r0 /* invalidate d-cache */
mtspr L1CSR1,%r0 /* invalidate i-cache */
mfspr %r1,DBSR
mtspr DBSR,%r1 /* Clear all valid bits */
/* Enable L1 Caches early */
lis %r2,[EMAIL PROTECTED] /* enable parity */
ori %r2,%r2,L1CSR0_DCE
mtspr L1CSR0,%r2 /* enable L1 Dcache */
isync
mtspr L1CSR1,%r2 /* enable L1 Icache */
isync
sync
########################################################################
#
# Clear and set up some registers - CCSRBAR use default value
########################################################################
#
li %r0,0x0000
lis %r1,0xffff
mtspr DEC, %r0 /* prevent dec
exceptions */
mttbl %r0 /* prevent fit &
wdt exceptions */
mttbu %r0
mtspr TSR, %r1 /* clear all timer
exception status */
mtspr TCR, %r0 /* disable all - Disable
WDT */
mtspr ESR, %r0 /* clear exception
syndrome register */
mtspr MCSR,%r0 /* machine check
syndrome register */
mtxer %r0 /* clear integer
exception register */
mtspr MMUCSR0, %r1 /* invalidate all tlb's
*/
/* Enable Time Base and Select Time Base Clock */
lis %r0,[EMAIL PROTECTED] /* Enable
machine check */
ori %r0, %r0, [EMAIL PROTECTED] /*Only For e500V2
Processors*/
ori %r0, %r0,[EMAIL PROTECTED] /* Enable Timebase */
mtspr HID0, %r0
/* create a temp mapping in AS=1 to the boot window */
lis %r6, [EMAIL PROTECTED]
ori %r6, %r6, [EMAIL PROTECTED]
lis %r7, [EMAIL PROTECTED]
ori %r7, %r7, [EMAIL PROTECTED]
lis %r8, [EMAIL PROTECTED]
ori %r8, %r8, [EMAIL PROTECTED]
lis %r9, [EMAIL PROTECTED]
ori %r9, %r9, [EMAIL PROTECTED]
mtspr MAS0,%r6
mtspr MAS1,%r7
mtspr MAS2,%r8
mtspr MAS3,%r9
isync
msync
tlbwe
tlbre
/* create a temp mapping in AS=1 to the stack */
lis %r6, [EMAIL PROTECTED]
ori %r6, %r6, [EMAIL PROTECTED]
lis %r7, [EMAIL PROTECTED]
ori %r7, %r7, [EMAIL PROTECTED]
lis %r8, [EMAIL PROTECTED]
ori %r8, %r8, [EMAIL PROTECTED]
lis %r9, [EMAIL PROTECTED]
ori %r9, %r9, [EMAIL PROTECTED]
mtspr MAS0,%r6
mtspr MAS1,%r7
mtspr MAS2,%r8
mtspr MAS3,%r9
isync
msync
tlbwe
lis %r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|[EMAIL PROTECTED]
ori %r6,%r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|[EMAIL PROTECTED]
lis %r7,[EMAIL PROTECTED]
ori %r7,%r7,[EMAIL PROTECTED]
mtspr SRR0,%r7
mtspr SRR1,%r6
rfi
switch_as:
/* L1 DCache is used for initial RAM */
/* Allocate Initial RAM in data cache. */
lis %r3,[EMAIL PROTECTED]
ori %r3,%r3,[EMAIL PROTECTED]
mfspr %r2, L1CFG0
andi. %r2, %r2, 0x1ff
/* cache size * 1024 / (2 * L1 line size) */
slwi %r2, %r2, (10 - 1 - L1_CACHE_SHIFT)
mtctr %r2
li %r0,0
1:
dcbz %r0,%r3
dcbtls 0,%r0,%r3
addi %r3,%r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */
/* Calculate absolute address in FLASH and jump there
*/
/*--------------------------------------------------------------*/
lis %r3,[EMAIL PROTECTED]
ori %r3,%r3,[EMAIL PROTECTED]
addi %r3,%r3,_start_cont - _start + _START_OFFSET
mtlr %r3
blr
#-----------------------------------------------------
# Special sequence needed to update CCSRBAR itself
#-----------------------------------------------------
..globl setup_ccsrbar
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
setup_ccsrbar:
lis %r4, [EMAIL PROTECTED]
ori %r4, %r4, [EMAIL PROTECTED]
lis %r5, [EMAIL PROTECTED]
ori %r5, %r5, [EMAIL PROTECTED]
srwi %r6,%r5,12
stw %r6, 0(%r4)
isync
lis %r5, 0xffff
ori %r5,%r5,0xf000
lwz %r5, 0(%r5)
isync
lis %r3, [EMAIL PROTECTED]
lwz %r5, [EMAIL PROTECTED](%r3)
isync
blr
#endif
.text
.globl _start
_start:
.long 0xDEADBEEF
.align 4
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1
dcache*/
lis %r1,[EMAIL PROTECTED]
ori %r1,%r1,[EMAIL PROTECTED]
li %r0,0
stwu %r0,-4(%r1)
stwu %r0,-4(%r1) /* Terminate call chain */
stwu %r1,-8(%r1) /* Save back chain and move SP
*/
lis %r0,[EMAIL PROTECTED] /* Address of reset vector */
ori %r0,%r0,[EMAIL PROTECTED]
stwu %r1,-8(%r1) /* Save back chain and move SP
*/
stw %r0,+12(%r1) /* Save return addr (underflow
vect) */
#switch back to AS = 0
lis %r3,(MSR_CE|MSR_ME|MSR_DE)@h
ori %r3,%r3,(MSR_CE|MSR_ME|MSR_DE)@l
mtmsr %r3
isync
bl main # Jump to main()
exit:
b exit # If there is a return from main(), loop
forever
..globl mpc85xx_start_image
mpc85xx_start_image:
#----------------------------------------
# Disable D-cache
#----------------------------------------
mfspr %r4,L1CSR0
lis %r5,0
ori %r5,%r5,L1CSR0_DCE
andc %r4,%r4,%r5
mtspr L1CSR0,%r0
isync
#----------------------------------------
# Jump to image
#----------------------------------------
mtlr %r3
blr
.end # end of text section
Start.o
========
D:\MPC8568\bsp-freescale-cdsmpc8568_cpusub\cpusub\ppc\be\start.o:
file format elf32-powerpc
D:\MPC8568\bsp-freescale-cdsmpc8568_cpusub\cpusub\ppc\be\start.o
architecture: powerpc:common, flags 0x00000011:
HAS_RELOC, HAS_SYMS
start address 0x00000000
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000070 00000000 00000000 00000040 2**4
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
1 .data 00000000 00000000 00000000 000000b0 2**0
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000000 00000000 00000000 000000b0 2**0
ALLOC
3 .bootpg 000001c4 00000000 00000000 000000b0 2**0
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
4 .PPC.EMB.apuinfo 00000018 00000000 00000000 00000274 2**0
CONTENTS, READONLY
SYMBOL TABLE:
00000001 l *ABS* 00000000 PPC_CPUOP_ENABLED
00000001 l *ABS* 00000000 MPC8280
00000001 l *ABS* 00000000 BUILDENV_qss
00000001 l *ABS* 00000000 VARIANT_cpusub
00000001 l *ABS* 00000000 VARIANT_be
00000000 l d .text 00000000 .text
00000000 l d .data 00000000 .data
00000000 l d .bss 00000000 .bss
00000000 l d .bootpg 00000000 .bootpg
00000148 l .bootpg 00000000 switch_as
0000004c l .text 00000000 exit
00000000 l d .PPC.EMB.apuinfo 00000000 .PPC.EMB.apuinfo
00000000 g .bootpg 00000000 _start_e500
00000188 g .bootpg 00000000 setup_ccsrbar
00000010 g .text 00000000 _start_cont
00000000 g .text 00000000 _start
00000000 *UND* 00000000 main
00000050 g .text 00000000 mpc85xx_start_image
Disassembly of section .text:
00000000 <_start>:
0: de ad be ef .long 0xdeadbeef
4: 60 00 00 00 nop
8: 60 00 00 00 nop
c: 60 00 00 00 nop
00000010 <_start_cont>:
10: 3c 20 e4 01 lis r1,-7167
14: 60 21 3f 80 ori r1,r1,16256
18: 38 00 00 00 li r0,0
1c: 94 01 ff fc stwu r0,-4(r1)
20: 94 01 ff fc stwu r0,-4(r1)
24: 94 21 ff f8 stwu r1,-8(r1)
28: 3c 00 ff ff lis r0,-1
2c: 60 00 ff fc ori r0,r0,65532
30: 94 21 ff f8 stwu r1,-8(r1)
34: 90 01 00 0c stw r0,12(r1)
38: 3c 60 00 02 lis r3,2
3c: 60 63 12 00 ori r3,r3,4608
40: 7c 60 01 24 mtmsr r3
44: 4c 00 01 2c isync
48: 48 00 00 01 bl 48 <_start_cont+0x38>
48: R_PPC_REL24 main
0000004c <exit>:
4c: 48 00 00 00 b 4c <exit>
00000050 <mpc85xx_start_image>:
50: 7c 92 fa a6 mfdbcr0 r4
54: 3c a0 00 00 lis r5,0
58: 60 a5 00 01 ori r5,r5,1
5c: 7c 84 28 78 andc r4,r4,r5
60: 7c 12 fb a6 mtdbcr0 r0
64: 4c 00 01 2c isync
68: 7c 68 03 a6 mtlr r3
6c: 4e 80 00 20 blr
Disassembly of section .bootpg:
00000000 <_start_e500>:
0: 48 00 00 01 bl 0 <_start_e500>
0: R_PPC_REL24 setup_ccsrbar
4: 3c c0 10 0c lis r6,4108
8: 60 c6 00 00 ori r6,r6,0
c: 3c e0 c0 00 lis r7,-16384
10: 60 e7 05 00 ori r7,r7,1280
14: 3d 00 e0 00 lis r8,-8192
18: 61 08 00 08 ori r8,r8,8
1c: 3d 20 e0 00 lis r9,-8192
20: 61 29 00 15 ori r9,r9,21
24: 7c d0 9b a6 mtspr 624,r6
28: 7c f1 9b a6 mtspr 625,r7
2c: 7d 12 9b a6 mtspr 626,r8
30: 7d 33 9b a6 mtspr 627,r9
34: 4c 00 01 2c isync
38: 7c 00 04 ac sync
3c: 7c 00 07 a4 tlbwehi r0,r0
40: 7c 00 07 64 tlbrehi r0,r0
44: 38 00 00 02 li r0,2
48: 7c 12 fb a6 mtdbcr0 r0
4c: 7c 13 fb a6 mtspr 1011,r0
50: 7c 30 4a a6 mfspr r1,304
54: 7c 30 4b a6 mtspr 304,r1
58: 3c 40 00 01 lis r2,1
5c: 60 42 00 01 ori r2,r2,1
60: 7c 52 fb a6 mtdbcr0 r2
64: 4c 00 01 2c isync
68: 7c 53 fb a6 mtspr 1011,r2
6c: 4c 00 01 2c isync
70: 7c 00 04 ac sync
74: 38 00 00 00 li r0,0
78: 3c 20 ff ff lis r1,-1
7c: 7c 16 03 a6 mtdec r0
80: 7c 1c 43 a6 mtsprg 4,r0
84: 7c 1d 43 a6 mtsprg 5,r0
88: 7c 30 53 a6 mtspr 336,r1
8c: 7c 14 53 a6 mtspr 340,r0
90: 7c 1e 0b a6 mtspr 62,r0
94: 7c 1c 8b a6 mtspr 572,r0
98: 7c 01 03 a6 mtxer r0
9c: 7c 34 fb a6 mtiac1 r1
a0: 3c 00 80 00 lis r0,-32768
a4: 60 00 00 80 ori r0,r0,128
a8: 60 00 40 00 ori r0,r0,16384
ac: 7c 10 fb a6 mtdbsr r0
b0: 3c c0 10 0f lis r6,4111
b4: 60 c6 00 00 ori r6,r6,0
b8: 3c e0 c0 00 lis r7,-16384
bc: 60 e7 17 00 ori r7,r7,5888
c0: 3d 00 ff 00 lis r8,-256
c4: 61 08 00 0a ori r8,r8,10
c8: 3d 20 ff 00 lis r9,-256
cc: 61 29 00 15 ori r9,r9,21
d0: 7c d0 9b a6 mtspr 624,r6
d4: 7c f1 9b a6 mtspr 625,r7
d8: 7d 12 9b a6 mtspr 626,r8
dc: 7d 33 9b a6 mtspr 627,r9
e0: 4c 00 01 2c isync
e4: 7c 00 04 ac sync
e8: 7c 00 07 a4 tlbwehi r0,r0
ec: 7c 00 07 64 tlbrehi r0,r0
f0: 3c c0 10 0e lis r6,4110
f4: 60 c6 00 00 ori r6,r6,0
f8: 3c e0 c0 00 lis r7,-16384
fc: 60 e7 12 00 ori r7,r7,4608
100: 3d 00 e4 01 lis r8,-7167
104: 61 08 00 00 ori r8,r8,0
108: 3d 20 e4 01 lis r9,-7167
10c: 61 29 00 15 ori r9,r9,21
110: 7c d0 9b a6 mtspr 624,r6
114: 7c f1 9b a6 mtspr 625,r7
118: 7d 12 9b a6 mtspr 626,r8
11c: 7d 33 9b a6 mtspr 627,r9
120: 4c 00 01 2c isync
124: 7c 00 04 ac sync
128: 7c 00 07 a4 tlbwehi r0,r0
12c: 3c c0 00 02 lis r6,2
130: 60 c6 12 30 ori r6,r6,4656
134: 3c e0 00 00 lis r7,0
136: R_PPC_ADDR16_HI .bootpg+0x148
138: 60 e7 01 48 ori r7,r7,328
13a: R_PPC_ADDR16_LO .bootpg+0x148
13c: 7c fa 03 a6 mtsrr0 r7
140: 7c db 03 a6 mtsrr1 r6
144: 4c 00 00 64 rfi
00000148 <switch_as>:
148: 3c 60 e4 01 lis r3,-7167
14c: 60 63 00 00 ori r3,r3,0
150: 7c 43 82 a6 mfspr r2,515
154: 70 42 01 ff andi. r2,r2,511
158: 54 42 20 36 rlwinm r2,r2,4,0,27
15c: 7c 49 03 a6 mtctr r2
160: 38 00 00 00 li r0,0
164: 7c 00 1f ec dcbz r0,r3
168: 7c 00 19 4c .long 0x7c00194c
16c: 38 63 00 20 addi r3,r3,32
170: 42 00 ff f4 bdnz+ 164 <switch_as+0x1c>
174: 3c 60 ff f8 lis r3,-8
178: 60 63 00 00 ori r3,r3,0
17c: 38 63 00 10 addi r3,r3,16
180: 7c 68 03 a6 mtlr r3
184: 4e 80 00 20 blr
00000188 <setup_ccsrbar>:
188: 3c 80 ff 70 lis r4,-144
18c: 60 84 00 00 ori r4,r4,0
190: 3c a0 e0 00 lis r5,-8192
194: 60 a5 00 00 ori r5,r5,0
198: 54 a6 a3 3e rlwinm r6,r5,20,12,31
19c: 90 c4 00 00 stw r6,0(r4)
1a0: 4c 00 01 2c isync
1a4: 3c a0 ff ff lis r5,-1
1a8: 60 a5 f0 00 ori r5,r5,61440
1ac: 80 a5 00 00 lwz r5,0(r5)
1b0: 4c 00 01 2c isync
1b4: 3c 60 e0 00 lis r3,-8192
1b8: 80 a3 00 00 lwz r5,0(r3)
1bc: 4c 00 01 2c isync
1c0: 4e 80 00 20 blr
Linker Code
===========
OUTPUT_ARCH(powerpc)
SECTIONS
{
.resetvec 0xFFFFFFFC:
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000:
{
start.o (.bootpg)
} = 0xffff
.text 0xFFF80000:
{
start.o (.text)
board.o (.text)
main.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
Thanks & Regards,
Vignesh Kumar B
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