On 08:10 Wed 28 Jan , Maxim Artamonov wrote: > V3 NAND_SPL support for phycore imx31 > > This patch is applied on U-Boot v2008.10 release. > > Changelog: > > * Added infinitive loop for ecc-error cases; > * Correct to code-style; > * Was changed mx31_nand_data_output function for support 2-k > NAND page chips (Magnus Lilja proposal); > * Was changed name of CFG_NAND_PAGE_COUNT by > CFG_NAND_PAGES_PER_BLOCK; > > > V2 NAND_SPL support for phycore imx31 > > > > Changelog: > > > > * Added bad block verify & skip; > > * Correct to code-style; > > * Added few comments; > > >> V1 nand booting support (SPL) for phyCORE-i.MX31 > >> > >> This patch allows Phytec phyCORE-i.MX31 based > >> system to boot from embed NAND-flash memory. > >> It not add support for NAND cmd and/or driver > >> for U-BOOT, it is only SPL for U-BOOT. For NAND > >> support in U-BOOT I give refer to Magnus Lilja's > >> aug/2008 patch series for PDK/Litekit boards. > >> ("[U-Boot] [PATCH v3 4/6] i.MX31: Add i.MX31 > >> NAND Flash Controller driver."; MID 1219998982- > >> 21289-5-git-send-email-lilja.mag...@gmail.com) > >> > >> Some note: by default, Phytec phyCORE-i.MX31 > >> board (pcm-037 on pcm-970) is not suitable > >> for nand-bootloading, because of SW5 switchers > >> block haven't appropriate modes(8-bit, 2k page > >> or 16-bit, 512B page) for BOOTPINS[4:0] and > >> nand-flash(8-bit mode, 512B page) contemporary. > >> There is require to make RESOLDER for really > >> nand-booting either BOOTPIN state or JN1/2 and > >> RN41/42. > >> > >> This nand-spl work with 8-bit, 512B page size nand-flash. > > Signed-off-by: Maxim Artamonov <scn1874 at yandex.ru> > --- > MAKEALL | 1 + > Makefile | 9 ++- > board/imx31_phycore/config.mk | 10 ++ > board/imx31_phycore/lowlevel_init.S | 27 ++++- > board/imx31_phycore/u-boot-nand.lds | 62 ++++++++++ > cpu/arm1136/start.S | 36 ++++-- > include/asm-arm/arch-mx31/mx31-regs.h | 96 +++++++++++++++ > include/configs/imx31_phycore.h | 33 +++++ > nand_spl/board/imx31_phycore/Makefile | 95 +++++++++++++++ > nand_spl/board/imx31_phycore/config.mk | 33 +++++ > nand_spl/board/imx31_phycore/u-boot.lds | 65 ++++++++++ > nand_spl/nand_boot_mx31.c | 200 > +++++++++++++++++++++++++++++++ > 12 files changed, 656 insertions(+), 11 deletions(-) > create mode 100644 board/imx31_phycore/u-boot-nand.lds > create mode 100644 nand_spl/board/imx31_phycore/Makefile > create mode 100644 nand_spl/board/imx31_phycore/config.mk > create mode 100644 nand_spl/board/imx31_phycore/u-boot.lds > create mode 100644 nand_spl/nand_boot_mx31.c > > diff --git a/MAKEALL b/MAKEALL > index 9ccb9ac..1f639a8 100755 > --- a/MAKEALL > +++ b/MAKEALL > @@ -522,6 +522,7 @@ LIST_ARM11=" \ > apollon \ > imx31_litekit \ > imx31_phycore \ > + imx31_phycore_nand \ > mx31ads \ > smdk6400 \ > " > diff --git a/Makefile b/Makefile > index 58b8331..7519dfe 100644 > --- a/Makefile > +++ b/Makefile > @@ -353,7 +353,7 @@ $(NAND_SPL): $(VERSION_FILE) > $(obj)include/autoconf.mk > $(MAKE) -C nand_spl/board/$(BOARDDIR) all > > $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk > - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > > $(obj)u-boot-nand.bin > + cat $(obj)nand_spl/u-boot-spl-aligned.bin $(obj)u-boot.bin > > $(obj)u-boot-nand.bin why? > > $(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk > $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all > @@ -2805,6 +2805,13 @@ imx31_litekit_config : unconfig > imx31_phycore_config : unconfig > @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31 > > +imx31_phycore_nand_config : unconfig > + @mkdir -p $(obj)include $(obj)board/imx31_phycore > + @mkdir -p $(obj)nand_spl/board/imx31_phycore > + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h > + @$(MKCONFIG) -n $@ -a imx31_phycore arm arm1136 imx31_phycore NULL mx31 > + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk > + > mx31ads_config : unconfig > @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31 > > diff --git a/board/imx31_phycore/config.mk b/board/imx31_phycore/config.mk > index d34dc02..412defc 100644 > --- a/board/imx31_phycore/config.mk > +++ b/board/imx31_phycore/config.mk > @@ -1 +1,11 @@ > +# > +# (C) Copyright 2008 > +# was changed by Maxim Artamonov, <scn1874 at yandex.ru> > +# > + > +ifndef CONFIG_NAND_SPL > TEXT_BASE = 0x87f00000 > +else > +TEXT_BASE = 0x87ec0000 > +endif > + > diff --git a/board/imx31_phycore/lowlevel_init.S > b/board/imx31_phycore/lowlevel_init.S > index c5d6eb0..afae317 100644 > --- a/board/imx31_phycore/lowlevel_init.S > +++ b/board/imx31_phycore/lowlevel_init.S > @@ -1,5 +1,7 @@ > /* > - * > + * (C) Copyright 2008 > + * Maxim Artamonov, <scn1874 at yandex.ru> > + * > * (c) 2007 Pengutronix, Sascha Hauer <s.ha...@pengutronix.de> > * > * See file CREDITS for list of people who contributed to this > @@ -43,6 +45,20 @@ > bcs 1b > .endm > > +#ifdef CONFIG_NAND_SPL > +/* somewhat macro to reduce bin size for CONFIG_NAND_SPL*/ > +.macro FILLREGS begreg, val, count, step > + ldr r2, =\begreg > + ldr r3, =\val > + ldr r4, =\count > +2: > + str r3, [r2] > + add r2, r2, #\step > + subs r4, r4, #1 > + bcs 2b > +.endm > +#endif > + > .globl lowlevel_init > lowlevel_init: > > @@ -60,10 +76,18 @@ lowlevel_init: > > REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) > > +#ifdef CONFIG_NAND_SPL > + FILLREGS 0x43FAC26C, 0, 0x3, 0x4 > +#else > REG 0x43FAC26C, 0 /* SDCLK */ > REG 0x43FAC270, 0 /* CAS */ > REG 0x43FAC274, 0 /* RAS */ > +#endif /* CONFIG_NAND_SPL */ > REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ > + > +#ifdef CONFIG_NAND_SPL > + FILLREGS 0x43FAC284, 0, 0x17, 0x4 > +#else > REG 0x43FAC284, 0 /* DQM3 */ > REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 > (0x288..0x2DC) */ > REG 0x43FAC28C, 0 > @@ -87,6 +111,7 @@ lowlevel_init: > REG 0x43FAC2D4, 0 > REG 0x43FAC2D8, 0 > REG 0x43FAC2DC, 0 > +#endif /* CONFIG_NAND_SPL */ > REG 0xB8001010, 0x00000004 > REG 0xB8001004, 0x006ac73a > REG 0xB8001000, 0x92100000 > diff --git a/board/imx31_phycore/u-boot-nand.lds > b/board/imx31_phycore/u-boot-nand.lds > new file mode 100644 > index 0000000..bd09a8d > --- /dev/null > +++ b/board/imx31_phycore/u-boot-nand.lds > @@ -0,0 +1,62 @@ > +/* > + * (C) Copyright 2008 > + * Maxim Artamonov, <scn1874 at yandex.ru> > + * > + * January 2004 - Changed to support H4 device > + * Copyright (c) 2004 Texas Instruments > + * > + * (C) Copyright 2002 > + * Gary Jennejohn, DENX Software Engineering, <g...@denx.de> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") > +OUTPUT_ARCH(arm) > +ENTRY(_start) > +SECTIONS > +{ > + . = 0x00000000; > + > + . = ALIGN(4); > + .text : > + { > + cpu/arm1136/start.o (.text) > + *(.text) > + } > + > + . = ALIGN(4); > + .rodata : { *(.rodata) } > + > + . = ALIGN(4); > + .data : { *(.data) } > + > + . = ALIGN(4); > + .got : { *(.got) } > + > + . = .; > + __u_boot_cmd_start = .; > + .u_boot_cmd : { *(.u_boot_cmd) } > + __u_boot_cmd_end = .; > + > + . = ALIGN(4); > + __bss_start = .; > + .bss : { *(.bss) } > + _end = .; > +} > diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S > index 51b664d..596efe9 100644 > --- a/cpu/arm1136/start.S > +++ b/cpu/arm1136/start.S > @@ -1,6 +1,9 @@ > /* > * armboot - Startup Code for OMP2420/ARM1136 CPU-core > * > + * > + * Copyright (c) 2008 Maxim Artamonov, <scn1874 at yandex.ru> > + * > * Copyright (c) 2004 Texas Instruments <r-woodru...@ti.com> > * > * Copyright (c) 2001 Marius Gr�ger <m...@sysgo.de> > @@ -32,6 +35,15 @@ > #include <version.h> > .globl _start > _start: b reset > +#ifdef CONFIG_NAND_SPL > + nop > + nop > + nop > + nop > + nop > + nop > + nop please use .rept to smplify it and make it more easier to read > +#else > #ifdef CONFIG_ONENAND_IPL > ldr pc, _hang > ldr pc, _hang > @@ -68,6 +80,7 @@ _irq: .word irq > _fiq: .word fiq > _pad: .word 0x12345678 /* now 16*4=64 */ > #endif /* CONFIG_ONENAND_IPL */ > +#endif /* CONFIG_NAND_SPL */ > .global _end_vect > _end_vect: > > @@ -156,9 +169,9 @@ relocate: /* relocate U-Boot to > RAM */ > adr r0, _start /* r0 <- current position of code */ > ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ > cmp r0, r1 /* don't reloc during debug */ > -#ifndef CONFIG_ONENAND_IPL > +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) > beq stack_setup > -#endif /* CONFIG_ONENAND_IPL */ > +#endif /* !CONFIG_ONENAND_IPL && !CONFIG_NAND_SPL*/ > > ldr r2, _armboot_start > ldr r3, _bss_start > @@ -175,7 +188,7 @@ copy_loop: > /* Set up the stack */ > stack_setup: > ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ > -#ifdef CONFIG_ONENAND_IPL > +#if defined(CONFIG_ONENAND_IPL) || defined (CONFIG_NAND_SPL) > sub sp, r0, #128 /* leave 32 words for abort-stack */ > #else > sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ > @@ -184,14 +197,14 @@ stack_setup: > sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) > #endif > sub sp, r0, #12 /* leave 3 words for abort-stack */ > -#endif /* CONFIG_ONENAND_IPL */ > +#endif /* CONFIG_ONENAND_IPL || CONFIG_NAND_SPL*/ > > clear_bss: > ldr r0, _bss_start /* find start of bss segment */ > ldr r1, _bss_end /* stop here */ > mov r2, #0x00000000 /* clear */ > > -#ifndef CONFIG_ONENAND_IPL > +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) > clbss_l:str r2, [r0] /* clear loop... */ > add r0, r0, #4 > cmp r0, r1 > @@ -200,12 +213,15 @@ clbss_l:str r2, [r0] /* clear > loop... */ > > ldr pc, _start_armboot > > +#ifdef CONFIG_NAND_SPL > +_start_armboot: .word nand_boot > +#else > #ifdef CONFIG_ONENAND_IPL > _start_armboot: .word start_oneboot > #else > _start_armboot: .word start_armboot > -#endif > - > +#endif /* CONFIG_ONENAND_IPL */ > +#endif /* CONFIG_NAND_SPL */ > > /* > ************************************************************************* > @@ -244,7 +260,7 @@ cpu_init_crit: > mov lr, ip /* restore link */ > mov pc, lr /* back to my caller */ > > -#ifndef CONFIG_ONENAND_IPL > +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) > /* > ************************************************************************* > * > @@ -357,11 +373,12 @@ cpu_init_crit: > .macro get_fiq_stack @ setup FIQ stack > ldr sp, FIQ_STACK_START > .endm > -#endif /* CONFIG_ONENAND_IPL */ > +#endif /* !CONFIG_ONENAND_IPL && !CONFIG_NAND_SPL*/ > > /* > * exception handlers > */ > +#ifndef CONFIG_NAND_SPL > #ifdef CONFIG_ONENAND_IPL why can can you have both at the sametime? > .align 5 > do_hang: > @@ -436,3 +453,4 @@ arm1136_cache_flush: > mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache > mov pc, lr @ back to caller > #endif /* CONFIG_ONENAND_IPL */ > +#endif /* !CONFIG_NAND_SPL*/ > diff --git a/include/asm-arm/arch-mx31/mx31-regs.h > b/include/asm-arm/arch-mx31/mx31-regs.h > index b04a718..78825f5 100644 > --- a/include/asm-arm/arch-mx31/mx31-regs.h > +++ b/include/asm-arm/arch-mx31/mx31-regs.h > @@ -168,4 +168,100 @@ > #define CS5_BASE 0xB6000000 > #define PCMCIA_MEM_BASE 0xC0000000 > > +/* > + * NAND controller > + */ > +#define NFC_BASE_ADDR 0xB8000000 > + > +/* > + * Addresses for NFC registers > + */ > +#define NFC_BUF_SIZE (*((volatile u16 *)(NFC_BASE_ADDR + 0xE00))) ^^^^^^^^^^^^ whitespace please fix and the other define have the same think please fix it too > +#define NFC_BUF_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE04))) > +#define NFC_FLASH_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE06))) > +#define NFC_FLASH_CMD (*((volatile u16 *)(NFC_BASE_ADDR + 0xE08))) > +#define NFC_CONFIG (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0A))) > +#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0C))) > +#define NFC_RSLTMAIN_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0E))) > +#define NFC_RSLTSPARE_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE10))) > +#define NFC_WRPROT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE12))) > +#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE14))) > +#define NFC_UNLOCKEND_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE16))) > +#define NFC_NF_WRPRST (*((volatile u16 *)(NFC_BASE_ADDR + 0xE18))) > +#define NFC_CONFIG1 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1A))) > +#define NFC_CONFIG2 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1C))) > + > +/* > + * Addresses for NFC RAM BUFFER Main area 0 > + */ > +#define MAIN_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x000) > +#define MAIN_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x200) > +#define MAIN_AREA2 (volatile u16 *)(NFC_BASE_ADDR + 0x400) > +#define MAIN_AREA3 (volatile u16 *)(NFC_BASE_ADDR + 0x600) > + > +/* > + * Addresses for NFC SPARE BUFFER Spare area 0 > + */ > +#define SPARE_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x800) > +#define SPARE_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x810) > +#define SPARE_AREA2 (volatile u16 *)(NFC_BASE_ADDR + 0x820) > +#define SPARE_AREA3 (volatile u16 *)(NFC_BASE_ADDR + 0x830) > + > +/* > + * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command > + * operation > + */ > +#define NFC_CMD 0x1 > + > +/* > + * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address > + * operation > + */ > +#define NFC_ADDR 0x2 > + > +/* > + * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input > + * operation > + */ > +#define NFC_INPUT 0x4 > + > +/* > + * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data > + * Output operation > + */ > +#define NFC_OUTPUT 0x8 > + > +/* > + * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID > + * operation > + */ > +#define NFC_ID 0x10 > + > +/* > + * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read > + * Status operation > + */ > +#define NFC_STATUS 0x20 > + > +/* > + * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status > + * operation > + */ > +#define NFC_INT 0x8000 > + > +#define NFC_SP_EN (1 << 2) > +#define NFC_ECC_EN (1 << 3) > +#define NFC_INT_MSK (1 << 4) > +#define NFC_BIG (1 << 5) > +#define NFC_RST (1 << 6) > +#define NFC_CE (1 << 7) > +#define NFC_ONE_CYCLE (1 << 8) > + > +/* > + * NFMS bit in RCSR register for pagesize of nandflash > + */ > +#define NFMS (*((volatile u32 *)CCM_RCSR)) > +#define NFMS_BIT 30 > + > #endif /* __ASM_ARCH_MX31_REGS_H */ > + > diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h > index 1540203..44ffaf3 100644 > --- a/include/configs/imx31_phycore.h > +++ b/include/configs/imx31_phycore.h > @@ -1,4 +1,7 @@ > /* > + * (C) Copyright 2008 > + * Maxim Artamonov, <scn1874 at yandex.ru> > + * > * (C) Copyright 2004 > * Texas Instruments. > * Richard Woodruff <r-woodru...@ti.com> > @@ -34,6 +37,11 @@ > #define CONFIG_MX31_HCLK_FREQ 26000000 > #define CONFIG_MX31_CLK32 32000 > > +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) > +#define CONFIG_SKIP_LOWLEVEL_INIT > +#define CONFIG_SKIP_RELOCATE_UBOOT > +#endif > + > #define CONFIG_DISPLAY_CPUINFO > #define CONFIG_DISPLAY_BOARDINFO > > @@ -172,6 +180,31 @@ > #define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ why? against which version of u-boot did create this patch? normaly all the CFG_ have been rename in CONFIG_SYS_ and btw please add a space before and after the '*-/+' & co > #define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ > > +/*----------------------------------------------------------------------- > + * NAND flash > + */ > + > +#define NAND_MAX_CHIPS 1 > +#define CFG_MAX_NAND_DEVICE 1 > +#define CFG_NAND_BASE 0x40000000 > + > +/* > + * Because of small buffer size of NFC in iMX31, SPL has to fit into 2kB. > + */ > + > +/*CFG_NAND_U_BOOT_OFFS and CFG_NAND_U_BOOT_SIZE must be align to full > pages*/ > +#define CFG_NAND_U_BOOT_OFFS 0x800 > +#define CFG_NAND_U_BOOT_SIZE 0x30000 > +#define CFG_NAND_U_BOOT_DST 0x87f00000 /* Load big U-Boot to > this addr */ > +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start big > U-Boot from */ > +#define CFG_NAND_SPL_DST CFG_NAND_U_BOOT_DST-0x40000 /* Relocate > NAND_SPL to this adress*/ please be carefull of the 80 chars limit > + > +#define CFG_NAND_PAGE_SIZE 0x200 > +#define CFG_NAND_BLOCK_SIZE 0x4000 > +#define CFG_NAND_PAGES_PER_BLOCK 0x20 > +/*for NAND_SPL*/ > +#define CFG_NAND_CHIP_SIZE 0x4000000 > + > /* > * JFFS2 partitions > */ > diff --git a/nand_spl/board/imx31_phycore/Makefile > b/nand_spl/board/imx31_phycore/Makefile > new file mode 100644 > index 0000000..0aabea3 > --- /dev/null > +++ b/nand_spl/board/imx31_phycore/Makefile > @@ -0,0 +1,95 @@ > +# > +# (C) Copyright 2008 > +# Maxim Artamonov, <scn1874 at yandex.ru> > +# > +# (C) Copyright 2006-2007 > +# Stefan Roese, DENX Software Engineering, s...@denx.de. > +# > +# (C) Copyright 2008 > +# Guennadi Liakhovetki, DENX Software Engineering, <l...@denx.de> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +CONFIG_NAND_SPL = y > + > +include $(TOPDIR)/config.mk > +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk > + > +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds > +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) > $(PLATFORM_LDFLAGS) > +AFLAGS += -DCONFIG_NAND_SPL > +CFLAGS += -DCONFIG_NAND_SPL > + > +SOBJS = start.o lowlevel_init.o > +COBJS = nand_boot_mx31.o > + > +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) > +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) > +__OBJS := $(SOBJS) $(COBJS) why? > +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) > + > +nandobj := $(OBJTREE)/nand_spl/ > + > +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin > $(nandobj)u-boot-spl-aligned.bin > + > +all: $(obj).depend $(ALL) > + > +$(nandobj)u-boot-spl-aligned.bin: $(nandobj)u-boot-spl > + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ why ${}? > + > +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl > + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ > + > +$(nandobj)u-boot-spl: $(OBJS) > + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ > + -Map $(nandobj)u-boot-spl.map \ > + -o $(nandobj)u-boot-spl > + > +# create symbolic links for common files > + > +# from cpu directory > +$(obj)start.S: > + @rm -f $@ > + @ln -s $(TOPDIR)/cpu/arm1136/start.S $@ > + > +# from board directory > +$(obj)lowlevel_init.S: > + @rm -f $@ > + @ln -s $(TOPDIR)/board/imx31_phycore/lowlevel_init.S $@ > + > +# from nand_spl directory > +$(obj)nand_boot_mx31.c: > + @rm -f $@ > + @ln -s $(TOPDIR)/nand_spl/nand_boot_mx31.c $@ > + > +######################################################################### > + > +$(obj)%.o: $(obj)%.S > + $(CC) $(AFLAGS) -c -o $@ $< > + > +$(obj)%.o: $(obj)%.c > + $(CC) $(CFLAGS) -c -o $@ $< > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/nand_spl/board/imx31_phycore/config.mk > b/nand_spl/board/imx31_phycore/config.mk > new file mode 100644 > index 0000000..4c271c5 > --- /dev/null > +++ b/nand_spl/board/imx31_phycore/config.mk > @@ -0,0 +1,33 @@ > +# > +# (C) Copyright 2008 > +# Maxim Artamonov, <scn1874 at yandex.ru> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > +# phyCORE-i.MX31 - PHYTEC’s phyCORE Single Board Computer module > + > +# TEXT_BASE for SPL: = CFG_NAND_U_BOOT_DST-0x40000 is set in > board/imx31_phycore/config.mk > + > +# PAD_TO used to generate a 2kByte binary needed for the combined image > +# -> PAD_TO = TEXT_BASE + 2048 > +PAD_TO := $(shell expr $$[$(TEXT_BASE) + 2048]) > + > +ifeq ($(debug),1) > +PLATFORM_CPPFLAGS += -DDEBUG > +endif why? > diff --git a/nand_spl/board/imx31_phycore/u-boot.lds > b/nand_spl/board/imx31_phycore/u-boot.lds > new file mode 100644 > index 0000000..d25abf8 > --- /dev/null > +++ b/nand_spl/board/imx31_phycore/u-boot.lds > @@ -0,0 +1,65 @@ > +/* > + * > + * (C) Copyright 2008 > + * Maxim Artamonov, <scn1874 at yandex.ru> > + * > + * January 2004 - Changed to support H4 device > + * Copyright (c) 2004 Texas Instruments <snip> > +#include <common.h> > +#include <nand.h> > +#include <asm-arm/arch/mx31-regs.h> > + > +static void mx31_wait_ready(void) > +{ > + while (1) { > + if (NFC_CONFIG2 & NFC_INT) { > + NFC_CONFIG2 = NFC_CONFIG2 & (~NFC_INT);/* int flag > reset */ > + break; > + } > + } do we really nead an infinit loop? > +} > + > +static void mx31_nand_init(void) > +{ > + /* unlocking RAM Buff */ > + NFC_CONFIG = 0x2; please use readx/writex instead of direct access
please double check the whitespace and the coding tks Scott could you ack the nand part please Best Regards, J. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot