Not only Spansion supports the Persistent Protection Bits (PPB) locking. Other devices like the Micron JS28F512M29EWx also support this type of locking/unlocking. Detection of support is done in the same way as done for the Spansion chips - via the 0x49 CFI word.
This patch enables this PPB protection mechanism for all AMD type (AMD commandset) chips. Signed-off-by: Stefan Roese <[email protected]> Cc: Anatolij Gustschin <[email protected]> Cc: Holger Brunck <[email protected]> --- drivers/mtd/cfi_flash.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 045cf4a..5176d62 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1511,7 +1511,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) 0, ATM_CMD_UNLOCK_SECT); } } - if (manufact_match(info, AMD_MANUFACT)) { + if (info->legacy_unlock) { int flag = disable_interrupts(); int lock_flag; @@ -1741,12 +1741,9 @@ static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); #ifdef CONFIG_SYS_FLASH_PROTECTION - if (info->ext_addr && manufact_match(info, AMD_MANUFACT)) { - ushort spus; - - /* read sector protect/unprotect scheme */ - spus = flash_read_uchar(info, info->ext_addr + 9); - if (spus == 0x8) + if (info->ext_addr) { + /* read sector protect/unprotect scheme (at 0x49) */ + if (flash_read_uchar(info, info->ext_addr + 9) == 0x8) info->legacy_unlock = 1; } #endif @@ -2162,7 +2159,7 @@ ulong flash_get_size (phys_addr_t base, int banknum) break; case CFI_CMDSET_AMD_EXTENDED: case CFI_CMDSET_AMD_STANDARD: - if (!manufact_match(info, AMD_MANUFACT)) { + if (!info->legacy_unlock) { /* default: not protected */ info->protect[sect_cnt] = 0; break; -- 1.8.0.1 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
