With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to resolves this issue.
Signed-off-by: Ajay Kumar <ajaykumar...@samsung.com>
---
arch/arm/cpu/armv7/exynos/clock.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..bfcd5f7 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void)
*/
cfg = readl(&clk->src_disp1_0);
cfg &= ~(0xf);
- cfg |= 0x8;
+ cfg |= 0x6;
writel(cfg, &clk->src_disp1_0);
/*
--
1.7.1
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
