On 01/08/2013 12:18 PM, R Sricharan wrote:
> Introduce a weak version of dram_bank_setup function
> to allow a platform specific redefinition.
>
> This is used in the subsequent patch to setup dram region
> without 'XN' attribute in order to enable the region
> under client permissions.
>
> Signed-off-by: R Sricharan <[email protected]>
> Cc: Vincent Stehle <[email protected]>
> Cc: Tom Rini <[email protected]>
> ---
> arch/arm/include/asm/cache.h | 1 +
> arch/arm/lib/cache-cp15.c | 7 ++++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
> index eef6a5a..93811d2 100644
> --- a/arch/arm/include/asm/cache.h
> +++ b/arch/arm/include/asm/cache.h
> @@ -42,6 +42,7 @@ static inline void invalidate_l2_cache(void)
> void l2_cache_enable(void);
> void l2_cache_disable(void);
>
> +void dram_bank_mmu_setup(int bank);
> /*
> * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
> * use that value for aligning DMA buffers unless the board config has
> specified
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index 6edf815..843078e 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -23,6 +23,8 @@
>
> #include <common.h>
> #include <asm/system.h>
> +#include <asm/cache.h>
> +#include <linux/compiler.h>
>
> #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
>
> @@ -77,7 +79,7 @@ void mmu_set_region_dcache_behaviour(u32 start, int size,
> mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
> }
>
> -static inline void dram_bank_mmu_setup(int bank)
> +void __dram_bank_mmu_setup(int bank)
> {
> bd_t *bd = gd->bd;
> int i;
> @@ -94,6 +96,9 @@ static inline void dram_bank_mmu_setup(int bank)
> }
> }
>
> +void dram_bank_mmu_setup(int bank)
> + __attribute__((weak, alias("__dram_bank_mmu_setup")));
Please use this instead (you already included linux/compiler.h for this):
__weak void dram_bank_mmu_setup(int bank)
{
...
Thanks,
Stefan
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