Dear Haiying Wang, In message <[email protected]> you wrote: > There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of > LBCR > in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then > invalidate it after LBCR bit 13 is set. > > Signed-off-by: Haiying Wang <[email protected]> ... > --- a/cpu/mpc85xx/start.S > +++ b/cpu/mpc85xx/start.S ... > + lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h > + ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l > + > + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h > + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l > + > + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, > (MAS3_SX|MAS3_SW|MAS3_SR))@h > + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, > (MAS3_SX|MAS3_SW|MAS3_SR))@l
Lines too long. > diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c > index 58340c1..be43a3e 100644 > --- a/drivers/misc/fsl_law.c > +++ b/drivers/misc/fsl_law.c > @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; ... > +#if defined(CONFIG_MPC8569) > + uint plppar1; /* 0xe0040 - Platform port pin assignment > register 1 */ > + uint plppar2; /* 0xe0044 - Platform port pin assignment > register 2 */ > + uint plpdir1; /* 0xe0048 - Platform port pin direction > register 1 */ > + uint plpdir2; /* 0xe004c - Platform port pin direction > register 2 */ > +#else Lines too long. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected] The thing is, as you progress in the Craft, you'll learn there is another rule... When you break rules, break 'em good and hard. - Terry Pratchett, _Wyrd Sisters_ _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
