Hi Stefano,
this one too ;-)
> The VDDMEM ramped up in very weird way as it was horribly misconfigured.
> Instead of setting up VDDMEM in one swipe, let it rise slowly the same
> way as VDDD and VDDA in spl_power_init.c and then only clear ILIMIT before
> memory gets inited. This makes sure the VDDMEM rises sanely, not jumps up
> and down as it did till now.
>
> The VDDMEM prior to this change did this:
> 2V0____ .--------2V5
>
> | `--'
>
> 0V____|
>
> The VDDMEM now does this:
> 2V0_____,-----------2V5
> /
> 0V__|
>
> Moreover, VDDIO on MX23 uses 25mV steps while MX28 uses 50mV steps,
> fix this difference too.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Fabio Estevam <fabio.este...@freescale.com>
> Cc: Otavio Salvador <ota...@ossystems.com.br>
> Cc: Stefano Babic <sba...@denx.de>
> ---
> arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 12 ++-----
> arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 50
> +++++++++++++++++++++------ 2 files changed, 42 insertions(+), 20
> deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index bc2d69c..19dd8fb 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> @@ -234,17 +234,9 @@ static void mx23_mem_setup_vddmem(void)
> struct mxs_power_regs *power_regs =
> (struct mxs_power_regs *)MXS_POWER_BASE;
>
> - writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
> - POWER_VDDMEMCTRL_ENABLE_ILIMIT |
> - POWER_VDDMEMCTRL_ENABLE_LINREG |
> - POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
> - &power_regs->hw_power_vddmemctrl);
> + clrbits_le32(&power_regs->hw_power_vddmemctrl,
> + POWER_VDDMEMCTRL_ENABLE_ILIMIT);
>
> - early_delay(10000);
> -
> - writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
> - POWER_VDDMEMCTRL_ENABLE_LINREG,
> - &power_regs->hw_power_vddmemctrl);
> }
>
> static void mx23_mem_init(void)
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
> b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 287c698..21cac7b
> 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
> @@ -687,6 +687,12 @@ static void mxs_power_configure_power_source(void)
> mxs_init_batt_bo();
>
> mxs_switch_vddd_to_dcdc_source();
> +
> +#ifdef CONFIG_MX23
> + /* Fire up the VDDMEM LinReg now that we're all set. */
> + writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
> + &power_regs->hw_power_vddmemctrl);
> +#endif
> }
>
> static void mxs_enable_output_rail_protection(void)
> @@ -781,7 +787,11 @@ struct mxs_vddx_cfg {
> static const struct mxs_vddx_cfg mxs_vddio_cfg = {
> .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
> hw_power_vddioctrl),
> +#if defined(CONFIG_MX23)
> + .step_mV = 25,
> +#else
> .step_mV = 50,
> +#endif
> .lowest_mV = 2800,
> .powered_by_linreg = mxs_get_vddio_power_source_off,
> .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
> @@ -804,6 +814,21 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = {
> .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
> };
>
> +#ifdef CONFIG_MX23
> +static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
> + .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
> + hw_power_vddmemctrl),
> + .step_mV = 50,
> + .lowest_mV = 1700,
> + .powered_by_linreg = NULL,
> + .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
> + .bo_irq = 0,
> + .bo_enirq = 0,
> + .bo_offset_mask = 0,
> + .bo_offset_offset = 0,
> +};
> +#endif
> +
> static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
> uint32_t new_target, uint32_t new_brownout)
> {
> @@ -821,9 +846,10 @@ static void mxs_power_set_vddx(const struct
> mxs_vddx_cfg *cfg, cur_target += cfg->lowest_mV;
>
> adjust_up = new_target > cur_target;
> - powered_by_linreg = cfg->powered_by_linreg();
> + if (cfg->powered_by_linreg)
> + powered_by_linreg = cfg->powered_by_linreg();
>
> - if (adjust_up) {
> + if (adjust_up && cfg->bo_irq) {
> if (powered_by_linreg) {
> bo_int = readl(cfg->reg);
> clrbits_le32(cfg->reg, cfg->bo_enirq);
> @@ -864,14 +890,16 @@ static void mxs_power_set_vddx(const struct
> mxs_vddx_cfg *cfg, cur_target += cfg->lowest_mV;
> } while (new_target > cur_target);
>
> - if (adjust_up && powered_by_linreg) {
> - writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
> - if (bo_int & cfg->bo_enirq)
> - setbits_le32(cfg->reg, cfg->bo_enirq);
> - }
> + if (cfg->bo_irq) {
> + if (adjust_up && powered_by_linreg) {
> + writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
> + if (bo_int & cfg->bo_enirq)
> + setbits_le32(cfg->reg, cfg->bo_enirq);
> + }
>
> - clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
> - new_brownout << cfg->bo_offset_offset);
> + clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
> + new_brownout << cfg->bo_offset_offset);
> + }
> }
>
> static void mxs_setup_batt_detect(void)
> @@ -910,7 +938,9 @@ void mxs_power_init(void)
>
> mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
> mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
> -
> +#ifdef CONFIG_MX23
> + mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
> +#endif
> writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
> POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
> POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
Best regards,
Marek Vasut
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