Hello, I have been working for a while trying to port U-Boot over to a MIPS AR7161 SoC chip. The actual product is a Buffalo WZR-HP-AG300H router. I have been making quite a bit of successful progress, bu the two FLASH chip archetecture is throwing me off a little. There are two FLASH chips, 16MiB W25Q128BV. The first FLASH chip is where U-Boot resides and is mapped to 0xBF000000 to 0xBFFFFFFF. The second FLASH chip is suppsed to map to 0xBE000000 to 0xBEFFFFFF.
I have been successful in modifying the driver (with a few glitches that I am still fixing) to support the second chip. Since the FLASH is SPI based, the first or second chip is selected with a CS line, which I added support for in the driver. The two chips are detected properly at startup, and the size is correct, however, the mapping (KSEG1?) is mapping only the first chip, and I have been looking for how to get the second chip mapped. I think it has to do with the lowlevel init functions, but am difficulty understanding where the FLASH is mapped. I am fairly sure I have the low level setup correct, PLL, DDR, etc, which took a little work since I can't locate any techinical manuals for this chip, I had to go off reverse engineering the registers based on other ar71xx based boards. The original bootloader maps these correctly, and in openocd I can read data from the second FLASH chip. However, when I run the new bootloader I am working on the addresses are not mapped correctly for the second FLASH chip, even in openocd. Any assistance would be appreciated. When I get something working a little better I would like to contribute the results. Allan _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
