>>>>> "Ilya" == Ilya Ledvich <[email protected]> writes:
Ilya> Fix the wrong mapping between the DDR I/O control registers on Ilya> AM33XX SoCs and the software representation in the SPL code. The Ilya> most recent public TRM defines the following DDR I/O control Ilya> registers offsets: Ilya> * ddr_cmd0_ioctrl : offset 0x44E11404 Ilya> * ddr_cmd1_ioctrl : offset 0x44E11408 Ilya> * ddr_cmd2_ioctrl : offset 0x44E1140C Ilya> * ddr_data0_ioctrl: offset 0x44E11440 Ilya> * ddr_data1_ioctrl: offset 0x44E11444 Ilya> While the struct ddr_cmdtctrl has also some reserved bits in the Ilya> beginning. The struct is mapped to the address 0x44E11404. As a Ilya> result "cm0ioctl" points to the ddr_cmd1_ioctrl register, Ilya> "cm1ioctl" to the ddr_cmd2_ioctrl and etc. Registers Ilya> ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because Ilya> of this mapping mismatch. Ilya> Signed-off-by: Ilya Ledvich <[email protected]> Reviewed-by: Peter Korsgaard <[email protected]> -- Bye, Peter Korsgaard _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
