Dear Prafulla Wadaskar, In message <[email protected]> you wrote: > This is ARM v5TE-compliant processor core with > MMU and L1/L2 Cache > > Signed-off-by: prafulla_wadaskar <[email protected]> > Reviewed by: Ronen Shitrit <[email protected]> > --- > cpu/arm926ejs/start.S | 5 +++++ > 1 files changed, 5 insertions(+), 0 deletions(-) > > diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S > index ed4932a..08ec955 100644 > --- a/cpu/arm926ejs/start.S > +++ b/cpu/arm926ejs/start.S > @@ -214,10 +214,15 @@ cpu_init_crit: > * disable MMU stuff and caches > */ > mrc p15, 0, r0, c1, c0, 0 > +#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) > + bic r0, r0, #0x00000007 /* clear bits 2:0 (CAM) */ > + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ > +#else > bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ > bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ > orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ > orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ > +#endif > mcr p15, 0, r0, c1, c0, 0
Why is this special case needed? Cannot you enable the IC, too? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected] Voodoo Programming: Things programmers do that they know shouldn't work but they try anyway, and which sometimes actually work, such as recompiling everything. - Karl Lehenbauer _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
