Thank you Scott. On a somehow related question, when I use "cpu X release" to run some code on a core other than 0, the changes to memory made by cpu X are not made visible globally. I believe this is connected with WIMGE bits - as soon as disable L1 and L2 it works fine - am I correct? If so, does core 0 have 0x00000000 - 0x3FFFFFFF and 0x40000000 - 0x7FFFFFFF TLB entries marked as cache coherent, or do I also have to set them for it?
João On Tue, Jul 2, 2013 at 11:11 PM, Scott Wood <[email protected]> wrote: > On 07/02/2013 07:02:21 AM, João Fernandes wrote: > >> As the subject says, I'm trying to run the "Hello world" standalone >> application example on a core other than 0, on a Freescale QorIQ P4080. >> >> I tried through the shell and programmatically by exporting cpu_release >> function... nothing. My first thought was that only core 0 has register r2 >> with the address of the "global_data" structure, so I tried to set it on >> the other cores, but still nothing. Help on this matter is highly >> appreciated. >> > > If you mean a U-Boot application, this is not supported. U-Boot doesn't > run on cores other than 0, except for a small stub for the spin table code. > > If you have true standalone code, you can release it on other CPUs using > the "cpu <n> release" command. That code will not have access to any > U-Boot functionality. Its entry state will be as described for secondary > CPUs in ePAPR. It will be the same as if an OS were spinning up its > secondary cores by writing directly to the spin table. > > -Scott >
_______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
