Hi, > On Thu, Jul 11, 2013 at 8:18 PM, Fabio Estevam <[email protected]> wrote: > > On Thu, Jul 11, 2013 at 8:03 PM, Marek Vasut <[email protected]> wrote: > >> The MX28 multi-layer AHB bus can be too slow and trigger the > >> FEC DMA too early, before all the data hit the DRAM. This patch > >> ensures the data are written in the RAM before the DMA starts. > >> Please see the comment in the patch for full details. > >> > >> This patch was produced with an amazing help from Albert Aribaud, > >> who pointed out it can possibly be such a bus synchronisation > >> issue. > >> > >> Signed-off-by: Marek Vasut <[email protected]> > >> Cc: Albert ARIBAUD <[email protected]> > >> Cc: Fabio Estevam <[email protected]> > >> Cc: Stefano Babic <[email protected]> > > > > Excellent, managed to transfer 90MB via TFTP on mx28evk without a > > single timeout. > > > > Tested-by: Fabio Estevam <[email protected]> > > It's working here too. > > Tested-by: Alexandre Pereira da Silva <[email protected]>
Nice to hear, thank Albert for finding this. Best regards, Marek Vasut _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
