Common Samsung code has been moved one level up - to ./samsung-common directory.
This would allow other - non S5P based targets to reuse this code base
Moreover duplicated header files were removed.
Signed-off-by: Lukasz Majewski <l.majew...@majess.pl>
---
Changes for v3:
- Comply with SPDX license format when moving files to new location
Changes for v2:
- Only compile in libsamsung-common for non arm9 boards
- Exclude common sromc controller code
- Adjust smdkc100 to work with common sromc.h header
- Adjust boards #includes for asm/samsung-common/sromc.h
---
Makefile | 7 +-
arch/arm/cpu/armv7/exynos/pinmux.c | 2 +-
arch/arm/cpu/armv7/s5p-common/Makefile | 34 ------
arch/arm/cpu/armv7/s5p-common/cpu_info.c | 41 -------
arch/arm/cpu/armv7/s5p-common/pwm.c | 171 --------------------------
arch/arm/cpu/armv7/s5p-common/sromc.c | 33 -----
arch/arm/cpu/armv7/s5p-common/timer.c | 132 --------------------
arch/arm/cpu/samsung-common/Makefile | 30 +++++
arch/arm/cpu/samsung-common/cpu_info.c | 40 +++++++
arch/arm/cpu/samsung-common/pwm.c | 172 +++++++++++++++++++++++++++
arch/arm/cpu/samsung-common/sromc.c | 33 +++++
arch/arm/cpu/samsung-common/timer.c | 131 ++++++++++++++++++++
arch/arm/include/asm/arch-exynos/pwm.h | 55 ---------
arch/arm/include/asm/arch-exynos/sromc.h | 55 ---------
arch/arm/include/asm/arch-s5pc1xx/pwm.h | 55 ---------
arch/arm/include/asm/arch-s5pc1xx/sromc.h | 40 -------
arch/arm/include/asm/samsung-common/pwm.h | 55 +++++++++
arch/arm/include/asm/samsung-common/sromc.h | 60 ++++++++++
board/samsung/smdk5250/exynos5-dt.c | 2 +-
board/samsung/smdkc100/smdkc100.c | 11 +-
board/samsung/smdkv310/smdkv310.c | 2 +-
spl/Makefile | 2 +-
22 files changed, 534 insertions(+), 629 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/s5p-common/Makefile
delete mode 100644 arch/arm/cpu/armv7/s5p-common/cpu_info.c
delete mode 100644 arch/arm/cpu/armv7/s5p-common/pwm.c
delete mode 100644 arch/arm/cpu/armv7/s5p-common/sromc.c
delete mode 100644 arch/arm/cpu/armv7/s5p-common/timer.c
create mode 100644 arch/arm/cpu/samsung-common/Makefile
create mode 100644 arch/arm/cpu/samsung-common/cpu_info.c
create mode 100644 arch/arm/cpu/samsung-common/pwm.c
create mode 100644 arch/arm/cpu/samsung-common/sromc.c
create mode 100644 arch/arm/cpu/samsung-common/timer.c
delete mode 100644 arch/arm/include/asm/arch-exynos/pwm.h
delete mode 100644 arch/arm/include/asm/arch-exynos/sromc.h
delete mode 100644 arch/arm/include/asm/arch-s5pc1xx/pwm.h
delete mode 100644 arch/arm/include/asm/arch-s5pc1xx/sromc.h
create mode 100644 arch/arm/include/asm/samsung-common/pwm.h
create mode 100644 arch/arm/include/asm/samsung-common/sromc.h
diff --git a/Makefile b/Makefile
index d545d30..836c04d 100644
--- a/Makefile
+++ b/Makefile
@@ -330,11 +330,10 @@ ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs
vf610))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
-ifeq ($(SOC),s5pc1xx)
-LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
+ifeq ($(VENDOR),samsung)
+ifneq ($(SOC), s3c24x0)
+LIBS-y += arch/$(ARCH)/cpu/samsung-common/libsamsung-common.o
endif
-ifeq ($(SOC),exynos)
-LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
endif
ifneq ($(CONFIG_TEGRA),)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 1b05ebf..ed662bb 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -9,7 +9,7 @@
#include <fdtdec.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/sromc.h>
+#include <asm/samsung-common/sromc.h>
static void exynos5_uart_config(int peripheral)
{
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile
b/arch/arm/cpu/armv7/s5p-common/Makefile
deleted file mode 100644
index fd7290c..0000000
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# Copyright (C) 2009 Samsung Electronics
-# Minkyu Kang <mk7.k...@samsung.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)libs5p-common.o
-
-COBJS-y += cpu_info.o
-ifndef CONFIG_SPL_BUILD
-COBJS-y += timer.o
-COBJS-y += sromc.o
-COBJS-$(CONFIG_PWM) += pwm.o
-endif
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c
b/arch/arm/cpu/armv7/s5p-common/cpu_info.c
deleted file mode 100644
index a8d91e7..0000000
--- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <mk7.k...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clk.h>
-
-/* Default is s5pc100 */
-unsigned int s5p_cpu_id = 0xC100;
-/* Default is EVT1 */
-unsigned int s5p_cpu_rev = 1;
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
- s5p_set_cpu_id();
-
- return 0;
-}
-#endif
-
-u32 get_device_type(void)
-{
- return s5p_cpu_id;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
- char buf[32];
-
- printf("CPU:\t%s%X@%sMHz\n",
- s5p_get_cpu_name(), s5p_cpu_id,
- strmhz(buf, get_arm_clk()));
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c
b/arch/arm/cpu/armv7/s5p-common/pwm.c
deleted file mode 100644
index 47aa9cc..0000000
--- a/arch/arm/cpu/armv7/s5p-common/pwm.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics
- *
- * Donghwa Lee <dh09....@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <pwm.h>
-#include <asm/io.h>
-#include <asm/arch/pwm.h>
-#include <asm/arch/clk.h>
-
-int pwm_enable(int pwm_id)
-{
- const struct s5p_timer *pwm =
- (struct s5p_timer *)samsung_get_base_timer();
- unsigned long tcon;
-
- tcon = readl(&pwm->tcon);
- tcon |= TCON_START(pwm_id);
-
- writel(tcon, &pwm->tcon);
-
- return 0;
-}
-
-void pwm_disable(int pwm_id)
-{
- const struct s5p_timer *pwm =
- (struct s5p_timer *)samsung_get_base_timer();
- unsigned long tcon;
-
- tcon = readl(&pwm->tcon);
- tcon &= ~TCON_START(pwm_id);
-
- writel(tcon, &pwm->tcon);
-}
-
-static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
-{
- unsigned long tin_parent_rate;
- unsigned int div;
-
- tin_parent_rate = get_pwm_clk();
-
- for (div = 2; div <= 16; div *= 2) {
- if ((tin_parent_rate / (div << 16)) < freq)
- return tin_parent_rate / div;
- }
-
- return tin_parent_rate / 16;
-}
-
-#define NS_IN_SEC 1000000000UL
-
-int pwm_config(int pwm_id, int duty_ns, int period_ns)
-{
- const struct s5p_timer *pwm =
- (struct s5p_timer *)samsung_get_base_timer();
- unsigned int offset;
- unsigned long tin_rate;
- unsigned long tin_ns;
- unsigned long frequency;
- unsigned long tcon;
- unsigned long tcnt;
- unsigned long tcmp;
-
- /*
- * We currently avoid using 64bit arithmetic by using the
- * fact that anything faster than 1GHz is easily representable
- * by 32bits.
- */
- if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0)
- return -ERANGE;
-
- if (duty_ns > period_ns)
- return -EINVAL;
-
- frequency = NS_IN_SEC / period_ns;
-
- /* Check to see if we are changing the clock rate of the PWM */
- tin_rate = pwm_calc_tin(pwm_id, frequency);
-
- tin_ns = NS_IN_SEC / tin_rate;
- tcnt = period_ns / tin_ns;
-
- /* Note, counters count down */
- tcmp = duty_ns / tin_ns;
- tcmp = tcnt - tcmp;
-
- /* Update the PWM register block. */
- offset = pwm_id * 3;
- if (pwm_id < 4) {
- writel(tcnt, &pwm->tcntb0 + offset);
- writel(tcmp, &pwm->tcmpb0 + offset);
- }
-
- tcon = readl(&pwm->tcon);
- tcon |= TCON_UPDATE(pwm_id);
- if (pwm_id < 4)
- tcon |= TCON_AUTO_RELOAD(pwm_id);
- else
- tcon |= TCON4_AUTO_RELOAD;
- writel(tcon, &pwm->tcon);
-
- tcon &= ~TCON_UPDATE(pwm_id);
- writel(tcon, &pwm->tcon);
-
- return 0;
-}
-
-int pwm_init(int pwm_id, int div, int invert)
-{
- u32 val;
- const struct s5p_timer *pwm =
- (struct s5p_timer *)samsung_get_base_timer();
- unsigned long ticks_per_period;
- unsigned int offset, prescaler;
-
- /*
- * Timer Freq(HZ) =
- * PWM_CLK / { (prescaler_value + 1) * (divider_value) }
- */
-
- val = readl(&pwm->tcfg0);
- if (pwm_id < 2) {
- prescaler = PRESCALER_0;
- val &= ~0xff;
- val |= (prescaler & 0xff);
- } else {
- prescaler = PRESCALER_1;
- val &= ~(0xff << 8);
- val |= (prescaler & 0xff) << 8;
- }
- writel(val, &pwm->tcfg0);
- val = readl(&pwm->tcfg1);
- val &= ~(0xf << MUX_DIV_SHIFT(pwm_id));
- val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
- writel(val, &pwm->tcfg1);
-
- if (pwm_id == 4) {
- /*
- * TODO(sjg): Use this as a countdown timer for now. We count
- * down from the maximum value to 0, then reset.
- */
- ticks_per_period = -1UL;
- } else {
- const unsigned long pwm_hz = 1000;
- unsigned long timer_rate_hz = get_pwm_clk() /
- ((prescaler + 1) * (1 << div));
-
- ticks_per_period = timer_rate_hz / pwm_hz;
- }
-
- /* set count value */
- offset = pwm_id * 3;
-
- writel(ticks_per_period, &pwm->tcntb0 + offset);
-
- val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
- if (invert && (pwm_id < 4))
- val |= TCON_INVERTER(pwm_id);
- writel(val, &pwm->tcon);
-
- pwm_enable(pwm_id);
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/s5p-common/sromc.c
b/arch/arm/cpu/armv7/s5p-common/sromc.c
deleted file mode 100644
index 806456f..0000000
--- a/arch/arm/cpu/armv7/s5p-common/sromc.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.nav...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sromc.h>
-
-/*
- * s5p_config_sromc() - select the proper SROMC Bank and configure the
- * band width control and bank control registers
- * srom_bank - SROM
- * srom_bw_conf - SMC Band witdh reg configuration value
- * srom_bc_conf - SMC Bank Control reg configuration value
- */
-void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
-{
- u32 tmp;
- struct s5p_sromc *srom =
- (struct s5p_sromc *)samsung_get_base_sromc();
-
- /* Configure SMC_BW register to handle proper SROMC bank */
- tmp = srom->bw;
- tmp &= ~(0xF << (srom_bank * 4));
- tmp |= srom_bw_conf;
- srom->bw = tmp;
-
- /* Configure SMC_BC register */
- srom->bc[srom_bank] = srom_bc_conf;
-}
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c
b/arch/arm/cpu/armv7/s5p-common/timer.c
deleted file mode 100644
index 5b87a08..0000000
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Heungjun Kim <riverful....@samsung.com>
- * Inki Dae <inki....@samsung.com>
- * Minkyu Kang <mk7.k...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/arch/pwm.h>
-#include <asm/arch/clk.h>
-#include <pwm.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long get_current_tick(void);
-
-/* macro to read the 16 bit timer */
-static inline struct s5p_timer *s5p_get_base_timer(void)
-{
- return (struct s5p_timer *)samsung_get_base_timer();
-}
-
-/**
- * Read the countdown timer.
- *
- * This operates at 1MHz and counts downwards. It will wrap about every
- * hour (2^32 microseconds).
- *
- * @return current value of timer
- */
-static unsigned long timer_get_us_down(void)
-{
- struct s5p_timer *const timer = s5p_get_base_timer();
-
- return readl(&timer->tcnto4);
-}
-
-int timer_init(void)
-{
- /* PWM Timer 4 */
- pwm_init(4, MUX_DIV_4, 0);
- pwm_config(4, 100000, 100000);
- pwm_enable(4);
-
- /* Use this as the current monotonic time in us */
- gd->arch.timer_reset_value = 0;
-
- /* Use this as the last timer value we saw */
- gd->arch.lastinc = timer_get_us_down();
- reset_timer_masked();
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long get_timer(unsigned long base)
-{
- unsigned long long time_ms;
-
- ulong now = timer_get_us_down();
-
- /*
- * Increment the time by the amount elapsed since the last read.
- * The timer may have wrapped around, but it makes no difference to
- * our arithmetic here.
- */
- gd->arch.timer_reset_value += gd->arch.lastinc - now;
- gd->arch.lastinc = now;
-
- /* Divide by 1000 to convert from us to ms */
- time_ms = gd->arch.timer_reset_value;
- do_div(time_ms, 1000);
- return time_ms - base;
-}
-
-unsigned long __attribute__((no_instrument_function)) timer_get_us(void)
-{
- static unsigned long base_time_us;
-
- struct s5p_timer *const timer =
- (struct s5p_timer *)samsung_get_base_timer();
- unsigned long now_downward_us = readl(&timer->tcnto4);
-
- if (!base_time_us)
- base_time_us = now_downward_us;
-
- /* Note that this timer counts downward. */
- return base_time_us - now_downward_us;
-}
-
-/* delay x useconds */
-void __udelay(unsigned long usec)
-{
- unsigned long count_value;
-
- count_value = timer_get_us_down();
- while ((int)(count_value - timer_get_us_down()) < (int)usec)
- ;
-}
-
-void reset_timer_masked(void)
-{
- struct s5p_timer *const timer = s5p_get_base_timer();
-
- /* reset time */
- gd->arch.lastinc = readl(&timer->tcnto4);
- gd->arch.tbl = 0;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-unsigned long get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/samsung-common/Makefile
b/arch/arm/cpu/samsung-common/Makefile
new file mode 100644
index 0000000..22eae3e
--- /dev/null
+++ b/arch/arm/cpu/samsung-common/Makefile
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2009 Samsung Electronics
+# Minkyu Kang <mk7.k...@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libsamsung-common.o
+
+COBJS-$(CONFIG_PWM) += pwm.o
+COBJS-y += timer.o sromc.o cpu_info.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/samsung-common/cpu_info.c
b/arch/arm/cpu/samsung-common/cpu_info.c
new file mode 100644
index 0000000..e18c4f6
--- /dev/null
+++ b/arch/arm/cpu/samsung-common/cpu_info.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.k...@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+
+/* Default is s5pc100 */
+unsigned int s5p_cpu_id = 0xC100;
+/* Default is EVT1 */
+unsigned int s5p_cpu_rev = 1;
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ s5p_set_cpu_id();
+
+ return 0;
+}
+#endif
+
+u32 get_device_type(void)
+{
+ return s5p_cpu_id;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ char buf[32];
+
+ printf("CPU:\t%s%X@%sMHz\n", s5p_get_cpu_name(), s5p_cpu_id,
+ strmhz(buf, get_arm_clk()));
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/samsung-common/pwm.c
b/arch/arm/cpu/samsung-common/pwm.c
new file mode 100644
index 0000000..d40af2f
--- /dev/null
+++ b/arch/arm/cpu/samsung-common/pwm.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Donghwa Lee <dh09....@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/samsung-common/pwm.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+
+int pwm_enable(int pwm_id)
+{
+ const struct s5p_timer *pwm =
+ (struct s5p_timer *)samsung_get_base_timer();
+ unsigned long tcon;
+
+ tcon = readl(&pwm->tcon);
+ tcon |= TCON_START(pwm_id);
+
+ writel(tcon, &pwm->tcon);
+
+ return 0;
+}
+
+void pwm_disable(int pwm_id)
+{
+ const struct s5p_timer *pwm =
+ (struct s5p_timer *)samsung_get_base_timer();
+ unsigned long tcon;
+
+ tcon = readl(&pwm->tcon);
+ tcon &= ~TCON_START(pwm_id);
+
+ writel(tcon, &pwm->tcon);
+}
+
+static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
+{
+ unsigned long tin_parent_rate;
+ unsigned int div;
+
+ tin_parent_rate = get_pwm_clk();
+
+ for (div = 2; div <= 16; div *= 2) {
+ if ((tin_parent_rate / (div << 16)) < freq)
+ return tin_parent_rate / div;
+ }
+
+ return tin_parent_rate / 16;
+}
+
+#define NS_IN_SEC 1000000000UL
+
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+ const struct s5p_timer *pwm =
+ (struct s5p_timer *)samsung_get_base_timer();
+ unsigned int offset;
+ unsigned long tin_rate;
+ unsigned long tin_ns;
+ unsigned long frequency;
+ unsigned long tcon;
+ unsigned long tcnt;
+ unsigned long tcmp;
+
+ /*
+ * We currently avoid using 64bit arithmetic by using the
+ * fact that anything faster than 1GHz is easily representable
+ * by 32bits.
+ */
+ if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0)
+ return -ERANGE;
+
+ if (duty_ns > period_ns)
+ return -EINVAL;
+
+ frequency = NS_IN_SEC / period_ns;
+
+ /* Check to see if we are changing the clock rate of the PWM */
+ tin_rate = pwm_calc_tin(pwm_id, frequency);
+
+ tin_ns = NS_IN_SEC / tin_rate;
+ tcnt = period_ns / tin_ns;
+
+ /* Note, counters count down */
+ tcmp = duty_ns / tin_ns;
+ tcmp = tcnt - tcmp;
+
+ /* Update the PWM register block. */
+ offset = pwm_id * 3;
+ if (pwm_id < 4) {
+ writel(tcnt, &pwm->tcntb0 + offset);
+ writel(tcmp, &pwm->tcmpb0 + offset);
+ }
+
+ tcon = readl(&pwm->tcon);
+ tcon |= TCON_UPDATE(pwm_id);
+ if (pwm_id < 4)
+ tcon |= TCON_AUTO_RELOAD(pwm_id);
+ else
+ tcon |= TCON4_AUTO_RELOAD;
+ writel(tcon, &pwm->tcon);
+
+ tcon &= ~TCON_UPDATE(pwm_id);
+ writel(tcon, &pwm->tcon);
+
+ return 0;
+}
+
+int pwm_init(int pwm_id, int div, int invert)
+{
+ u32 val;
+ const struct s5p_timer *pwm =
+ (struct s5p_timer *)samsung_get_base_timer();
+ unsigned long ticks_per_period;
+ unsigned int offset, prescaler;
+
+ /*
+ * Timer Freq(HZ) =
+ * PWM_CLK / { (prescaler_value + 1) * (divider_value) }
+ */
+
+ val = readl(&pwm->tcfg0);
+ if (pwm_id < 2) {
+ prescaler = PRESCALER_0;
+ val &= ~0xff;
+ val |= (prescaler & 0xff);
+ } else {
+ prescaler = PRESCALER_1;
+ val &= ~(0xff << 8);
+ val |= (prescaler & 0xff) << 8;
+ }
+ writel(val, &pwm->tcfg0);
+ val = readl(&pwm->tcfg1);
+ val &= ~(0xf << MUX_DIV_SHIFT(pwm_id));
+ val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
+ writel(val, &pwm->tcfg1);
+
+ if (pwm_id == 4) {
+ /*
+ * TODO(sjg): Use this as a countdown timer for now. We count
+ * down from the maximum value to 0, then reset.
+ */
+ ticks_per_period = -1UL;
+ } else {
+ const unsigned long pwm_hz = 1000;
+ unsigned long timer_rate_hz = get_pwm_clk() /
+ ((prescaler + 1) * (1 << div));
+
+ ticks_per_period = timer_rate_hz / pwm_hz;
+ }
+
+ /* set count value */
+ offset = pwm_id * 3;
+
+ writel(ticks_per_period, &pwm->tcntb0 + offset);
+
+ val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
+ if (invert && (pwm_id < 4))
+ val |= TCON_INVERTER(pwm_id);
+ writel(val, &pwm->tcon);
+
+ pwm_enable(pwm_id);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/samsung-common/sromc.c
b/arch/arm/cpu/samsung-common/sromc.c
new file mode 100644
index 0000000..522f4d9
--- /dev/null
+++ b/arch/arm/cpu/samsung-common/sromc.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.nav...@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/samsung-common/sromc.h>
+
+/*
+ * s5p_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM
+ * srom_bw_conf - SMC Band witdh reg configuration value
+ * srom_bc_conf - SMC Bank Control reg configuration value
+ */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
+{
+ u32 tmp;
+ struct s5p_sromc *srom =
+ (struct s5p_sromc *)samsung_get_base_sromc();
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom->bw;
+ tmp &= ~(0xF << (srom_bank * 4));
+ tmp |= srom_bw_conf;
+ srom->bw = tmp;
+
+ /* Configure SMC_BC register */
+ srom->bc[srom_bank] = srom_bc_conf;
+}
diff --git a/arch/arm/cpu/samsung-common/timer.c
b/arch/arm/cpu/samsung-common/timer.c
new file mode 100644
index 0000000..42c8c8d
--- /dev/null
+++ b/arch/arm/cpu/samsung-common/timer.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Heungjun Kim <riverful....@samsung.com>
+ * Inki Dae <inki....@samsung.com>
+ * Minkyu Kang <mk7.k...@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/samsung-common/pwm.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <pwm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* macro to read the 16 bit timer */
+static inline struct s5p_timer *s5p_get_base_timer(void)
+{
+ return (struct s5p_timer *)samsung_get_base_timer();
+}
+
+/**
+ * Read the countdown timer.
+ *
+ * This operates at 1MHz and counts downwards. It will wrap about every
+ * hour (2^32 microseconds).
+ *
+ * @return current value of timer
+ */
+static unsigned long timer_get_us_down(void)
+{
+ struct s5p_timer *const timer = s5p_get_base_timer();
+
+ return readl(&timer->tcnto4);
+}
+
+int timer_init(void)
+{
+ /* PWM Timer 4 */
+ pwm_init(4, MUX_DIV_4, 0);
+ pwm_config(4, 100000, 100000);
+ pwm_enable(4);
+
+ /* Use this as the current monotonic time in us */
+ gd->arch.timer_reset_value = 0;
+
+ /* Use this as the last timer value we saw */
+ gd->arch.lastinc = timer_get_us_down();
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long get_timer(unsigned long base)
+{
+ unsigned long long time_ms;
+
+ ulong now = timer_get_us_down();
+
+ /*
+ * Increment the time by the amount elapsed since the last read.
+ * The timer may have wrapped around, but it makes no difference to
+ * our arithmetic here.
+ */
+ gd->arch.timer_reset_value += gd->arch.lastinc - now;
+ gd->arch.lastinc = now;
+
+ /* Divide by 1000 to convert from us to ms */
+ time_ms = gd->arch.timer_reset_value;
+ do_div(time_ms, 1000);
+ return time_ms - base;
+}
+
+unsigned long __attribute__((no_instrument_function)) timer_get_us(void)
+{
+ static unsigned long base_time_us;
+
+ struct s5p_timer *const timer =
+ (struct s5p_timer *)samsung_get_base_timer();
+ unsigned long now_downward_us = readl(&timer->tcnto4);
+
+ if (!base_time_us)
+ base_time_us = now_downward_us;
+
+ /* Note that this timer counts downward. */
+ return base_time_us - now_downward_us;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+ unsigned long count_value;
+
+ count_value = timer_get_us_down();
+ while ((int)(count_value - timer_get_us_down()) < (int)usec)
+ ;
+}
+
+void reset_timer_masked(void)
+{
+ struct s5p_timer *const timer = s5p_get_base_timer();
+
+ /* reset time */
+ gd->arch.lastinc = readl(&timer->tcnto4);
+ gd->arch.tbl = 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/include/asm/arch-exynos/pwm.h
b/arch/arm/include/asm/arch-exynos/pwm.h
deleted file mode 100644
index 43474c3..0000000
--- a/arch/arm/include/asm/arch-exynos/pwm.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.p...@samsung.com>
- * Minkyu Kang <mk7.k...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PWM_H_
-#define __ASM_ARM_ARCH_PWM_H_
-
-#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
-#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
-
-/* Divider MUX */
-#define MUX_DIV_1 0 /* 1/1 period */
-#define MUX_DIV_2 1 /* 1/2 period */
-#define MUX_DIV_4 2 /* 1/4 period */
-#define MUX_DIV_8 3 /* 1/8 period */
-#define MUX_DIV_16 4 /* 1/16 period */
-
-#define MUX_DIV_SHIFT(x) (x * 4)
-
-#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
-
-#define TCON_START(x) (1 << TCON_OFFSET(x))
-#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
-#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
-#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
-#define TCON4_AUTO_RELOAD (1 << 22)
-
-#ifndef __ASSEMBLY__
-struct s5p_timer {
- unsigned int tcfg0;
- unsigned int tcfg1;
- unsigned int tcon;
- unsigned int tcntb0;
- unsigned int tcmpb0;
- unsigned int tcnto0;
- unsigned int tcntb1;
- unsigned int tcmpb1;
- unsigned int tcnto1;
- unsigned int tcntb2;
- unsigned int tcmpb2;
- unsigned int tcnto2;
- unsigned int tcntb3;
- unsigned int tcmpb3;
- unsigned int tcnto3;
- unsigned int tcntb4;
- unsigned int tcnto4;
- unsigned int tintcstat;
-};
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/arch-exynos/sromc.h
b/arch/arm/include/asm/arch-exynos/sromc.h
deleted file mode 100644
index 7f58403..0000000
--- a/arch/arm/include/asm/arch-exynos/sromc.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.nav...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Note: This file contains the register description for SROMC
- */
-
-#ifndef __ASM_ARCH_SROMC_H_
-#define __ASM_ARCH_SROMC_H_
-
-#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
-#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base
address*/
- /* 1-> Byte base address*/
-#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
-#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
-
-#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
-#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
-#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
-#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
-#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
-#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
-#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5p_sromc {
- unsigned int bw;
- unsigned int bc[4];
-};
-#endif /* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
-
-enum {
- FDT_SROM_PMC,
- FDT_SROM_TACP,
- FDT_SROM_TAH,
- FDT_SROM_TCOH,
- FDT_SROM_TACC,
- FDT_SROM_TCOS,
- FDT_SROM_TACS,
-
- FDT_SROM_TIMING_COUNT,
-};
-
-struct fdt_sromc {
- u8 bank; /* srom bank number */
- u8 width; /* bus width in bytes */
- unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
-};
-
-#endif /* __ASM_ARCH_SROMC_H_ */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h
b/arch/arm/include/asm/arch-s5pc1xx/pwm.h
deleted file mode 100644
index 7a33ed8..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.p...@samsung.com>
- * Minkyu Kang <mk7.k...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PWM_H_
-#define __ASM_ARM_ARCH_PWM_H_
-
-#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
-#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
-
-/* Divider MUX */
-#define MUX_DIV_1 0 /* 1/1 period */
-#define MUX_DIV_2 1 /* 1/2 period */
-#define MUX_DIV_4 2 /* 1/4 period */
-#define MUX_DIV_8 3 /* 1/8 period */
-#define MUX_DIV_16 4 /* 1/16 period */
-
-#define MUX_DIV_SHIFT(x) (x * 4)
-
-#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
-
-#define TCON_START(x) (1 << TCON_OFFSET(x))
-#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
-#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
-#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
-#define TCON4_AUTO_RELOAD (1 << 22)
-
-#ifndef __ASSEMBLY__
-struct s5p_timer {
- unsigned int tcfg0;
- unsigned int tcfg1;
- unsigned int tcon;
- unsigned int tcntb0;
- unsigned int tcmpb0;
- unsigned int tcnto0;
- unsigned int tcntb1;
- unsigned int tcmpb1;
- unsigned int tcnto1;
- unsigned int tcntb2;
- unsigned int tcmpb2;
- unsigned int tcnto2;
- unsigned int tcntb3;
- unsigned int res1;
- unsigned int tcnto3;
- unsigned int tcntb4;
- unsigned int tcnto4;
- unsigned int tintcstat;
-};
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/sromc.h
b/arch/arm/include/asm/arch-s5pc1xx/sromc.h
deleted file mode 100644
index df1bf51..0000000
--- a/arch/arm/include/asm/arch-s5pc1xx/sromc.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.nav...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Note: This file contains the register description for Memory subsystem
- * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
- *
- * Only SROMC is defined as of now
- */
-
-#ifndef __ASM_ARCH_SROMC_H_
-#define __ASM_ARCH_SROMC_H_
-
-#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
-#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
- /* 1-> Byte base address*/
-#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
-#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
-
-#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
-#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
-#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
-#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
-#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
-#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
-#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5p_sromc {
- unsigned int bw;
- unsigned int bc[6];
-};
-#endif /* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
-
-#endif /* __ASM_ARCH_SMC_H_ */
diff --git a/arch/arm/include/asm/samsung-common/pwm.h
b/arch/arm/include/asm/samsung-common/pwm.h
new file mode 100644
index 0000000..43474c3
--- /dev/null
+++ b/arch/arm/include/asm/samsung-common/pwm.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.p...@samsung.com>
+ * Minkyu Kang <mk7.k...@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1 0 /* 1/1 period */
+#define MUX_DIV_2 1 /* 1/2 period */
+#define MUX_DIV_4 2 /* 1/4 period */
+#define MUX_DIV_8 3 /* 1/8 period */
+#define MUX_DIV_16 4 /* 1/16 period */
+
+#define MUX_DIV_SHIFT(x) (x * 4)
+
+#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
+
+#define TCON_START(x) (1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD (1 << 22)
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+ unsigned int tcfg0;
+ unsigned int tcfg1;
+ unsigned int tcon;
+ unsigned int tcntb0;
+ unsigned int tcmpb0;
+ unsigned int tcnto0;
+ unsigned int tcntb1;
+ unsigned int tcmpb1;
+ unsigned int tcnto1;
+ unsigned int tcntb2;
+ unsigned int tcmpb2;
+ unsigned int tcnto2;
+ unsigned int tcntb3;
+ unsigned int tcmpb3;
+ unsigned int tcnto3;
+ unsigned int tcntb4;
+ unsigned int tcnto4;
+ unsigned int tintcstat;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm/include/asm/samsung-common/sromc.h
b/arch/arm/include/asm/samsung-common/sromc.h
new file mode 100644
index 0000000..2e3a99e
--- /dev/null
+++ b/arch/arm/include/asm/samsung-common/sromc.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.nav...@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Note: This file contains the register description for SROMC
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
+#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base
address*/
+ /* 1-> Byte base address*/
+#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
+#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
+
+#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
+#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
+#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
+#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
+#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
+#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
+#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+ unsigned int bw;
+#if defined(CONFIG_S5PC100) || defined(CONFIG_S5PC110)
+ unsigned int bc[4];
+#else
+ unsigned int bc[6];
+#endif
+};
+#endif /* __ASSEMBLY__ */
+
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+enum {
+ FDT_SROM_PMC,
+ FDT_SROM_TACP,
+ FDT_SROM_TAH,
+ FDT_SROM_TCOH,
+ FDT_SROM_TACC,
+ FDT_SROM_TCOS,
+ FDT_SROM_TACS,
+
+ FDT_SROM_TIMING_COUNT,
+};
+
+struct fdt_sromc {
+ u8 bank; /* srom bank number */
+ u8 width; /* bus width in bytes */
+ unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
+};
+
+#endif /* __ASM_ARCH_SROMC_H_ */
diff --git a/board/samsung/smdk5250/exynos5-dt.c
b/board/samsung/smdk5250/exynos5-dt.c
index bb4a82f..734183a 100644
--- a/board/samsung/smdk5250/exynos5-dt.c
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -18,7 +18,7 @@
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
-#include <asm/arch/sromc.h>
+#include <asm/samsung-common/sromc.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
#include <tmu.h>
diff --git a/board/samsung/smdkc100/smdkc100.c
b/board/samsung/smdkc100/smdkc100.c
index 860c851..1e481f9 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/sromc.h>
+#include <asm/samsung-common/sromc.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
@@ -28,10 +28,11 @@ static void smc9115_pre_init(void)
s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
- smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
- smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
- | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
- | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
+ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+ smc_bc_conf = SROMC_BC_TACS(0x0) | SROMC_BC_TCOS(0x4)
+ | SROMC_BC_TACC(0xe) | SROMC_BC_TCOH(0x1)
+ | SROMC_BC_TAH(0x4) | SROMC_BC_TACP(0x6)
+ | SROMC_BC_PMC(0x0);
/* Select and configure the SROMC bank */
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
diff --git a/board/samsung/smdkv310/smdkv310.c
b/board/samsung/smdkv310/smdkv310.c
index 81a3060..b85fe14 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -12,7 +12,7 @@
#include <asm/arch/mmc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/sromc.h>
+#include <asm/samsung-common/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
struct exynos4_gpio_part1 *gpio1;
diff --git a/spl/Makefile b/spl/Makefile
index 6e5299b..d7d7b40 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -102,7 +102,7 @@ LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
ifeq ($(SOC),exynos)
-LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
+LIBS-y += arch/$(ARCH)/cpu/samsung-common/libsamsung-common.o
endif
# Add GCC lib
--
1.7.10.4
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