On Wed, 2013-09-11 at 22:13 +0800, FengHua wrote:
>
>
> > -----原始邮件-----
> > 发件人: "Scott Wood" <[email protected]>
> > 发送时间: 2013年9月10日 星期二
> > 收件人: FengHua <[email protected]>
> > 抄送: [email protected], [email protected]
> > 主题: Re: Re: [U-Boot] [PATCH v5 1/4] core support of arm64
> >
> > On Sat, 2013-09-07 at 22:56 +0800, FengHua wrote:
> > > > ARM64, though I've got a patch coming that will make the check work with
> > > > arm64.
> > > >
> > > > Likewise elsewhere -- most if not all of the CONFIG_ARMV8 uses should be
> > > > CONFIG_ARM64.
> > > >
> > >
> > > Actually, the naming is so confusing. The directory's name is armv8,
> > > but it only represents aarch64 here. So, whether CONFIG_ARMV8 or
> > > CONFIG_ARM64 should be used
> > > is difficult to make decision.
> >
> > Files that are about 64-bit rather than armv8 should not go in the armv8
> > directory. E.g. relocate should be arch/arm/lib/relocate64.S.
> >
>
> crt0.S and relocate.S both could be moved to /arm/lib/ and renamed.
> Currently, I try to keep armv8 specific codes within armv8 directory
> and do not mixed with original arm code. Absolutely we should did so when
> armv9 coming.
crt0 and relocate should be in in lib now. The others can probably stay
in armv8 until we see what is different in armv9.
> > > > > +void v8_outer_cache_inval_range(u64 start, u64 end)
> > > > > + __attribute__((weak, alias("__v8_outer_cache_inval_range")));
> > > >
> > > > What level do you anticipate these being overriden at? Individual
> > > > chips? Why?
> > > It's socs. I don't know how the armv8 processor would like to be. It's
> > > just derived from __v7_outer_cache*.
> >
> > Is this for flushing caches that are outside the core? On powerpc you
> > could do that with architected instructions for a range flush -- is that
> > not the case with ARM? Do the IC/DC instructions not operate on caches
> > outside the core?
>
> I noticed that cache-pl310.c implements v7_outer_* functions.
> IC/DC instructions could maintain caches in cache hierarchy of armv8
> whatever the cache is outside the core or inside the core.
> But armv8 architecture reference manual(not totally completed) do not
> require all caches exist in the cache hierarchy. Maybe some processors
> have it's own cache level that is not maintained by IC/DC instructions.
> who knows.
> I keep this just because it existed in armv7.
I'd leave it out until a need is observed.
-Scott
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