> > > > Hi York, > > I double checked the offset address of GPIO, I found that the offset > > addresses of GPIO on the boards you mentioned above are all changed to > > 0x0, not 0xc00 according to the newest RM. > > I do found that the offset address is 0xc00 in some old RMs. > > You can find the newest RM here: > > For MPC8572: > > http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/ > > 200815/108253488/223469393/223503931/226628079/226445024/MPC8572ERM_Re > > v3_DRAFT1.pdf?nodeid=226438746&vernum=-2 > > For p1023: > > http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/ > > 200815/108253488/223469393/223506436/223521755/223743960/P1023RM_Mark- > > up.pdf?nodeid=229647544&vernum=-2 > > for 1020: > > http://compass.freescale.net/livelink/livelink/fetch/2001/3448/223475/ > > 200815/108253488/223469393/223506436/223522385/224515312/P1020RM_Rev6_ > > Mark-up.pdf?nodeid=228476444&vernum=-2 > > > > If the offset addresses on these boards were 0xc00, the driver is > > still wrong, because in that case The GPIO address should be: > CONFIG_SYS_IMMR + 0xc00, not CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00. > > (CONFIG_SYS_MPC85xx_GPIO_ADDR == CONFIG_SYS_IMMR + > CONFIG_SYS_MPC85xx_GPIO_OFFSET). > > > > So, please apply this patch, I need the GPIO driver to operate GPIO. > > > > > > > Please update the commit message to list all SoCs you have confirmed the > offset. And don't say "no reason to add 0xc00". The reason was clear when > the code was written. Reference manuals said so. > > York
OK, I will resend this patch once the offset is confirmed by the RM owner. Thanks, Yuantian _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
