Qiang, On 09/16/2013 02:27 AM, Zhao Qiang wrote: > Previously, the address of a requested capability is define like that > "#define PCI_DCR 0x78" > But, the addresses of capabilities is different with regard to PCIe revs. > So this method is not flexible. > > Now a function to get the address of a requested capability is added and used. > It can get the address dynamically by capability ID. > The step of this function: > 1. Read Status register in PCIe configuration space to confirm that > Capabilities List is valid. > 2. Find the address of Capabilities Pointer Register. > 3. Find the address of requested capability from the first capability. > > Signed-off-by: Zhao Qiang <b45...@freescale.com> > --- > Changes for v2: > -Put an variable into "#ifdef" and "#endif" > Changes for v3: > -Modify the patch description > > > arch/powerpc/include/asm/fsl_pci.h | 13 +------- > drivers/pci/fsl_pci_init.c | 44 +++++++++++++++++++------- > drivers/pci/pci.c | 65 > ++++++++++++++++++++++++++++++++++++++ > include/pci.h | 10 ++++++ > 4 files changed, 108 insertions(+), 24 deletions(-) > > diff --git a/arch/powerpc/include/asm/fsl_pci.h > b/arch/powerpc/include/asm/fsl_pci.h > index 90b0a2f..6b12afa 100644 > --- a/arch/powerpc/include/asm/fsl_pci.h > +++ b/arch/powerpc/include/asm/fsl_pci.h > @@ -32,22 +32,11 @@ > /* Freescale-specific PCI config registers */ > #define FSL_PCI_PBFR 0x44 > > -#ifdef CONFIG_SYS_FSL_PCI_VER_3_X > +#ifndef CONFIG_SYS_FSL_PCI_VER_3_X > /* Currently only the PCIe capability is used, so hardcode the offset. > * if more capabilities need to be justified, the capability link method > * should be applied here > */
Does these comment still apply after you remove almost everything? > -#define FSL_PCIE_CAP_ID 0x70 > -#define PCI_DCR 0x78 /* PCIe Device Control Register */ > -#define PCI_DSR 0x7a /* PCIe Device Status Register */ > -#define PCI_LSR 0x82 /* PCIe Link Status Register */ > -#define PCI_LCR 0x80 /* PCIe Link Control Register */ > -#else > -#define FSL_PCIE_CAP_ID 0x4c > -#define PCI_DCR 0x54 /* PCIe Device Control Register */ > -#define PCI_DSR 0x56 /* PCIe Device Status Register */ > -#define PCI_LSR 0x5e /* PCIe Link Status Register */ > -#define PCI_LCR 0x5c /* PCIe Link Control Register */ > #define FSL_PCIE_CFG_RDY 0x4b0 > #endif > #define FSL_PCI_CFG_READY 1 /* Endpoint: allow inbound configuration */ What is the base of your patch? I don't see this line in either master branch, or any of my branches. Can you rebase to master branch, or mpc85xx/next branch? York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
