On 10/18/2013 02:47 AM, Valentin Longchamp wrote: > If the DDR3 module supports industrial temperature range and requires > the x2 refresh rate for that temp range, the refresh period must be > 3.9us instead of 7.8 us. > > This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 > RAM chips (no module used, chips directly soldered on board with an SPD > EEPROM). > > Signed-off-by: Valentin Longchamp <[email protected]> > > --- > Changes in v4: None > Changes in v3: None > Changes in v2: > - when refresh rate gets halved for extended range temperature > operations, the srt bit in the mode register 2 is set. >
Applied to 85xx/next, pending merge to 85xx/master. York _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
