________________________________________ 寄件者: Stefan Agner [ste...@agner.ch] 寄件日期: 2014年2月15日 上午 06:52 收件者: u-boot@lists.denx.de; Jim Lin; Tom Warren; swar...@wwwdotorg.org; s...@chromium.org; d...@lynxeye.de 主旨: Re: [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3
Am 2014-02-14 23:45, schrieb Stefan Agner: > /* Select ULPI parallel interface */ > - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); > + if (!controller->has_hostpc) { > + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, > + PTS_ULPI << PTS_SHIFT); > + else > + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, > + PTS_ULPI << PTS_SHIFT); > > /* enable ULPI transceiver */ > setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); Ok, just noticed that we need to address the different USBD register layout on Tegra 2 here too. Furthermore, the code does not compile with Tegra 2 header file since the hostpc1_devlc field is missing there. The function ehci_get_port_speed uses a define and some calculation to work around this issue. Another solution would be to create a dummy field in the Tegra 2 USB register header file... Any thoughts on that? [Jim} Try use usbctlr->usb_cmd + HOSTPC1_DEVLC instead of usbctlr->hostpc1_devlc --nvpublic _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot