On Mon, Apr 07, 2014 at 04:41:46PM +0100, Paul Burton wrote: > The prior accesses to the descriptor rings & init block via cached > memory had a few issues: > > - The memory needs cache flushes or invalidation at the appropriate > times, but was not necessarily aligned on cache line boundaries. > This could lead to data being incorrectly lost or written back to > RAM at the wrong time. > > - There are points where ordering of writes to the memory is > important, but because it's cached memory the pcnet controller > would see cache lines written back ordered by address. This could > occasionally lead to hardware seeing descriptors in an incorrect > state. > > - Flushing the cache constantly is inefficient. > > So, to avoid all of those issues simply access the descriptors & init > block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is > used to do this (retrieving an address in kseg1) as I could see no > existing generic solution. Since the MIPS Malta board is the only user > of the pcnet driver, hopefully this doesn't matter. > > Signed-off-by: Paul Burton <[email protected]>
Applied to u-boot/master, thanks! -- Tom
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