Without this patch is DRAM size one line below DRAM: which is not nice Origin: I2C: ready DRAM: ECC disabled 1 GiB Now running in RAM - U-Boot at: 3ff59000 MMC: zynq_sdhci: 0
Fixed by this patch: I2C: ready DRAM: ECC disabled 1 GiB Now running in RAM - U-Boot at: 3ff59000 MMC: zynq_sdhci: 0 Using default environment Signed-off-by: Michal Simek <[email protected]> --- Based on http://patchwork.ozlabs.org/patch/347048/ --- arch/arm/cpu/armv7/zynq/ddrc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index e0ed3bfb4350..1ea086d52079 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -34,7 +34,7 @@ void zynq_ddrc_init(void) /* ECC is enabled when memory is in 16bit mode and it is enabled */ if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { - puts("Memory: ECC enabled\n"); + puts("ECC enabled "); /* * Clear the first 1MB because it is not initialized from * first stage bootloader. To get ECC to work all memory has @@ -42,6 +42,6 @@ void zynq_ddrc_init(void) */ memset((void *)0, 0, 1 * 1024 * 1024); } else { - puts("Memory: ECC disabled\n"); + puts("ECC disabled "); } } -- 1.8.2.3
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