From: Fabio Estevam <fabio.este...@freescale.com>
mx6sx does not have sata nor ipu blocks, so do not handle such clocks.
Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
---
Changes since v3:
- None
Changes since v2:
- None
Changes since v1:
- None
arch/arm/cpu/armv7/mx6/clock.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index d31fbbd..51c964c 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -437,6 +437,7 @@ static int enable_enet_pll(uint32_t en)
return 0;
}
+#ifndef CONFIG_MX6SX
static void ungate_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
@@ -445,6 +446,7 @@ static void ungate_sata_clock(void)
/* Enable SATA clock. */
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
+#endif
static void ungate_pcie_clock(void)
{
@@ -455,11 +457,13 @@ static void ungate_pcie_clock(void)
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
}
+#ifndef CONFIG_MX6SX
int enable_sata_clock(void)
{
ungate_sata_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
+#endif
int enable_pcie_clock(void)
{
@@ -491,7 +495,9 @@ int enable_pcie_clock(void)
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
/* Party time! Ungate the clock to the PCIe. */
+#ifndef CONFIG_MX6SX
ungate_sata_clock();
+#endif
ungate_pcie_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
@@ -573,6 +579,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
return 0;
}
+#ifndef CONFIG_MX6SX
void enable_ipu_clock(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -581,6 +588,7 @@ void enable_ipu_clock(void)
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
}
+#endif
/***************************************************/
U_BOOT_CMD(
--
1.8.3.2
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